A review of technologies and design techniques of millimeter-wave power amplifiers

his article reviews the state-of-the-art millimeter-wave (mm-wave) power amplifiers (PAs), focusing on broadband design techniques. An overview of the main solid-state technologies is provided, including Si, gallium arsenide (GaAs), GaN, and other III-V materials, and both field-effect and bipolar transistors. The most popular broadband design techniques are introduced, before critically comparing through the most relevant design examples found in the scientific literature. Given the wide breadth of applications that are foreseen to exploit the mm-wave spectrum, this contribution will represent a valuable guide for designers who need a single reference before adventuring in the challenging task of the mm-wave PA design

168-195 GHz Power Amplifier with Output Power Larger Than 18 dBm in BiCMOS Technology

This paper presents a 4-way combined G-band power amplifier (PA) fabricated with a 130-nm SiGe BiCMOS process. First, a single-ended PA based on the cascode topology (CT) is designed at 185 GHz, which consists of three stages to get an overall gain and an output power higher than 27 dB and 13 dBm, respectively. Then, a 4-way combiner/splitter was designed using low-loss transmission lines at 130-210 GHz. Finally, the combiner was loaded with four single-ended PAs to complete the design of a 4-way combined PA. The chip of the fabricated PA occupies an area of 1.35mm 2 . The realized PA shows a saturated output power of 18.1 dBm with a peak gain of 25.9 dB and power-added efficiency (PAE) of 3.5% at 185 GHz. A maximum output power of 18.7 dBm with PAE of 4.4% is achieved at 170 GHz. The 3-dB and 6-dB bandwidth of the PA are 27 and 42 GHz, respectively. In addition, the PA delivers a saturated output power higher than 18 dBm in the frequency range 140-186 GHz. To the best of our knowledge, the power reported in this paper is the highest for G-band SiGe BiCMOS PAs

Millimeter-Wave and Terahertz Transceivers in SiGe BiCMOS Technologies

This invited paper reviews the progress of silicon–germanium (SiGe) bipolar-complementary metal–oxide–semiconductor (BiCMOS) technology-based integrated circuits (ICs) during the last two decades. Focus is set on various transceiver (TRX) realizations in the millimeter-wave range from 60 GHz and at terahertz (THz) frequencies above 300 GHz. This article discusses the development of SiGe technologies and ICs with the latter focusing on the commercially most important applications of radar and beyond 5G wireless communications. A variety of examples ranging from 77-GHz automotive radar to THz sensing as well as the beginnings of 60-GHz wireless communication up to THz chipsets for 100-Gb/s data transmission are recapitulated. This article closes with an outlook on emerging fields of research for future advancement of SiGe TRX performance

Radio Frequency and Millimeter Wave Circuit Component Design with SiGe BiCMOS Technology

The objective of this research is to study and leverage the unique properties and advantages of silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) integrated circuit technologies to better design radio frequency (RF) and millimeter wave (mm-wave) circuit components. With recent developments, the high yield and modest cost silicon-based semiconductor technologies have proven to be attractive and cost-effective alternatives to high-performance III-V technology platforms. Between SiGe bipolar complementary metal-oxide-semiconductor (BiCMOS) technology and advanced RF complementary metal-oxide-semiconductor (CMOS) technology, the fundamental device-level differences between SiGe HBTs and field-effect transistors (FETs) grant SiGe HBTs clear advantages as well as unique design concerns. The work presented in this dissertation identifies several advantages and challenges on design using SiGe HBTs and provides design examples that exploit and address these unique benefits and problems with circuit component designs using SiGe HBTs.Ph.D

A Fully integrated D-band Direct-Conversion I/Q Transmitter and Receiver Chipset in SiGe BiCMOS Technology

This paper presents design and characterization of single-chip 110-170 GHz (D-band) direct conversion in-phase/quadrature-phase (I/Q) transmitter and receiver monolithic microwave integrated circuits (MMICs), realized in a 130 nm SiGe BiCMOS process with ft/fmax of 250 GHz/370 GHz. The chipset is suitable for low power wideband communication and can be used in both homodyne and heterodyne architectures. The Transmitter chip consists of a six-stage power amplifier, an I/Q modulator, and a LO multiplier chain. The LO multiplier chain consists of frequency sixtupler followed by a two-stage amplifier. It exhibits a single sideband conversion gain of 23 dB and saturated output power of 0 dBm. The 3 dB RF bandwidth is 31 GHz from 114 to 145 GHz. The receiver includes a low noise amplifier, I/Q demodulator and x6 multiplier chain at the LO port. The receiver provides a conversion gain of 27 dB and has a noise figure of 10 dB. It has 3 dB RF bandwidth of 28 GHz from 112-140 GHz. The transmitter and receiver have dc power consumption of 240 mW and 280 mW, respectively. The chip area of each transmitter and receiver circuit is 1.4 mm x 1.1 mm

Wideband Watt-Level Spatial Power-Combined Power Amplifier in SiGe BiCMOS Technology for Efficient mm-Wave Array Transmitters

The continued demand for high-speed wireless communications is driving the development of integrated high-power transmitters at millimeter wave (mm-Wave) frequencies. Si-based technologies allow achieving a high level of integration but usually provide insufficient generated RF power to compensate for the increased propagation and material losses at mm-Wave bands due to the relatively low breakdown voltage of their devices. This problem can be reduced significantly if one could combine the power of multiple active devices on each antenna element. However, conventional on-chip power combining networks have inherently high insertion losses reducing transmitter efficiency and limiting its maximum achievable output power.This work presents a non-conventional design approach for mm-Wave Si-based Watt-level power amplifiers that is based on novel power-combining architecture, where an array of parallel custom PA-cells suited on the same chip is interfaced to a single substrate integrated waveguide (to be a part of an antenna element). This allows one to directly excite TEm0 waveguide modes with high power through spatial power combining functionality, obviating the need for intermediate and potentially lossy on-chip power combiners. The proposed solution offers wide impedance bandwidth (50%) and low insertion losses (0.4 dB), which are virtually independent from the number of interfaced PA-cells. The work evaluates the scalability bounds of the architecture as well as discusses the critical effects of coupled non-identical PA-cells, which are efficiently reduced by employing on-chip isolation load resistors.The proposed architecture has been demonstrated through an example of the combined PA with four differential cascode PA-cells suited on the same chip, which is flip-chip interconnected to the combiner placed on a laminate. This design is implemented in a 0.25 um SiGe BiCMOS technology. The PA-cell has a wideband performance (38.6%) with both high peak efficiency (30%) and high saturated output power (24.9 dBm), which is the highest reported output power level obtained without the use of circuit-level power combining in Si-based technologies at Ka-band. In order to achieve the optimal system-level performance of the combined PA, an EM-circuit-thermal optimization flow has been proposed, which accounts for various multiphysics effects occurring in the joint structure. The final PA achieves the peak PAE of 26.7% in combination with 30.8 dBm maximum saturated output power, which is the highest achievable output power in practical applications, where the 50-Ohms load is placed on a laminate. The high efficiency (>20%) and output power (>29.8 dBm) over a wide frequency range (30%) exceed the state-of-the-art in Si-based PAs

Four-element phased-array beamformers and a self-interference canceling full-duplex transciver in 130-nm SiGe for 5G applications at 26 GHz

This thesis is on the design of radio-frequency (RF) integrated front-end circuits for next generation 5G communication systems. The demand for higher data rates and lower latency in 5G networks can only be met using several new technologies including, but not limited to, mm-waves, massive-MIMO, and full-duplex. Use of mm-waves provides more bandwidth that is necessary for high data rates at the cost of increased attenuation in air. Massive-MIMO arrays are required to compensate for this increased path loss by providing beam steering and array gain. Furthermore, full duplex operation is desirable for improved spectrum efficiency and reduced latency. The difficulty of full duplex operation is the self-interference (SI) between transmit (TX) and receive (RX) paths. Conventional methods to suppress this interference utilize either bulky circulators, isolators, couplers or two separate antennas. These methods are not suitable for fully-integrated full-duplex massive-MIMO arrays. This thesis presents circuit and system level solutions to the issues summarized above, in the form of SiGe integrated circuits for 5G applications at 26 GHz. First, a full-duplex RF front-end architecture is proposed that is scalable to massive-MIMO arrays. It is based on blind, RF self-interference cancellation that is applicable to single/shared antenna front-ends. A high resolution RF vector modulator is developed, which is the key building block that empowers the full-duplex frontend architecture by achieving better than state-of-the-art 10-b monotonic phase control. This vector modulator is combined with linear-in-dB variable gain amplifiers and attenuators to realize a precision self-interference cancellation circuitry. Further, adaptive control of this SI canceler is made possible by including an on-chip low-power IQ downconverter. It correlates copies of transmitted and received signals and provides baseband/dc outputs that can be used to adaptively control the SI canceler. The solution comes at the cost of minimal additional circuitry, yet significantly eases linearity requirements of critical receiver blocks at RF/IF such as mixers and ADCs. Second, to complement the proposed full-duplex front-end architecture and to provide a more complete solution, high-performance beamformer ICs with 5-/6- b phase and 3-/4-b amplitude control capabilities are designed. Single-channel, separate transmitter and receiver beamformers are implemented targeting massive- MIMO mode of operation, and their four-channel versions are developed for phasedarray communication systems. Better than state-of-the-art noise performance is obtained in the RX beamformer channel, with a full-channel noise figure of 3.3 d

KEY FRONT-END CIRCUITS IN MILLIMETER-WAVE SILICON-BASED WIRELESS TRANSMITTERS FOR PHASED-ARRAY APPLICATIONS

Millimeter-wave (mm-Wave) phased arrays have been widely used in numerous wireless systems to perform beam forming and spatial filtering that can enhance the equivalent isotropically radiated power (EIRP) for the transmitter (TX). Regarding the existing phased-array architectures, an mm-Wave transmitter includes several building blocks to perform the desired delivered power and phases for wireless communication. Power amplifier (PA) is the most important building block. It needs to offer several advantages, e.g., high efficiency, broadband operation and high linearity. With the recent escalation of interest in 5G wireless communication technologies, mm-Wave transceivers at the 5G frequency bands (e.g., 28 GHz, 37 GHz, 39 GHz, and 60 GHz) have become an important topic in both academia and industry. Thus, PA design is a critical obstacle due to the challenges associated with implementing wideband, highly efficient and highly linear PAs at mm-Wave frequencies. In this dissertation, we present several PA design innovations to address the aforementioned challenges. Additionally, phase shifter (PS) also plays a key role in a phased-array system, since it governs the beam forming quality and steering capabilities. A high-performance phase shifter should achieve a low insertion loss, a wide phase shifting range, dense phase shift angles, and good input/output matching.Ph.D

A linear high-efficiency millimeter-wave CMOS Doherty radiator leveraging on-antenna active load-modulation

This thesis presents a Doherty Radiator architecture that explores multi-feed antennas to achieve an on-antenna Doherty load modulation network and demonstrate high-speed high-efficiency transmission of wideband modulated signals. On the passive circuits, we exploit the multi-feed antenna concept to realize compact and high-efficiency on-antenna active load modulation for close-to-ideal Doherty operation, on-antenna power combining, and mm-Wave signal radiation. Moreover, we analyze the far-field transmission of the proposed Doherty Radiator and demonstrate its wide Field-of-View (FoV). On the active circuits, we employ a GHz-bandwidth adaptive biasing at the Doherty Auxiliary power amplifier (PA) path to enhance the Main/Auxiliary Doherty cooperation and appropriate turning-on/-off of the Auxiliary path. A proof-of-concept Doherty Radiator implemented in a 45nm CMOS SOI process over 62-68GHz exhibits a consistent 1.45-1.53× PAE enhancement at 6dB PBO over an idealistic class-B PA with the same PAE at P1dB. The measured Continuous-Wave (CW) performance at 65GHz demonstrates 19.4/19.2dBm PSAT/P1dB and achieves 27.5%/20.1% PAE at peak/6dB PBO, respectively. For single-carrier 1Gsym/s 64-QAM modulation, the Doherty Radiator shows average output power of 14.2dBm with an average 20.2% PAE and -26.7dB EVM without digital predistortion. Consistent EVMs are observed over the entire antenna FoV, demonstrating spatially undistorted transmission and constant Doherty PBO efficiency enhancement.M.S