431 research outputs found
Nanopower CMOS transponders for UHF and microwave RFID systems
At first, we present an analysis and a discussion of the design options and tradeoffs for a passive microwave transponder. We derive a set of criteria for the optimization of the voltage multiplier, the power matching network and the backscatter modulator in order to optimize the operating range. In order to match the strictly power requirements, the communication protocol between transponder and reader has been chosen in a convenient way, in order to make the architecture of the passive transponder very simple and then ultra-low-power. From the circuital point of view, the digital section has been implemented in subthreshold CMOS logic with very low supply voltage and clock frequency. We present different solutions to supply power to the transponder, in order to keep the power consumption in the deep sub-µW regime and to drastically reduce the huge sensitivity of the subthreshold logic to temperature and process variations. Moreover, a low-voltage and low-power EEPROM in a standard CMOS process has been implemented. Finally, we have presented the implementation of the entire passive transponder, operating in the UHF or microwave frequency range
Integrated Circuits for Programming Flash Memories in Portable Applications
Smart devices such as smart grids, smart home devices, etc. are infrastructure systems that connect the world around us more than before. These devices can communicate with each other and help us manage our environment. This concept is called the Internet of Things (IoT). Not many smart nodes exist that are both low-power and programmable. Floating-gate (FG) transistors could be used to create adaptive sensor nodes by providing programmable bias currents. FG transistors are mostly used in digital applications like Flash memories. However, FG transistors can be used in analog applications, too. Unfortunately, due to the expensive infrastructure required for programming these transistors, they have not been economical to be used in portable applications. In this work, we present low-power approaches to programming FG transistors which make them a good candidate to be employed in future wireless sensor nodes and portable systems. First, we focus on the design of low-power circuits which can be used in programming the FG transistors such as high-voltage charge pumps, low-drop-out regulators, and voltage reference cells. Then, to achieve the goal of reducing the power consumption in programmable sensor nodes and reducing the programming infrastructure, we present a method to program FG transistors using negative voltages. We also present charge-pump structures to generate the necessary negative voltages for programming in this new configuration
Addressing On-Chip Power Conversion and Dissipation Issues in Many-Core System-on-a-Chip based on Conventional Silicon and Emerging Nanotechnologies
Title from PDF of title page viewed August 27, 2018Dissertation advisor: Masud H ChowdhuryVitaIncludes bibliographical references (pages 158-163)Thesis (Ph.D.)--School of Computing and Engineering and Department of Physics and Astronomy. University of Missouri--Kansas City, 2017Integrated circuits (ICs) are moving towards system-on-a-chip (SOC) designs. SOC
allows various small and large electronic systems to be implemented in a single chip. This
approach enables the miniaturization of design blocks that leads to high density transistor
integration, faster response time, and lower fabrication costs. To reap the benefits of SOC
and uphold the miniaturization of transistors, innovative power delivery and power
dissipation management schemes are paramount. This dissertation focuses on on-chip
integration of power delivery systems and managing power dissipation to increase the
lifetime of energy storage elements. We explore this problem from two different angels:
On-chip voltage regulators and power gating techniques. On-chip voltage regulators reduce
parasitic effects, and allow faster and efficient power delivery for microprocessors. Power
gating techniques, on the other hand, reduce the power loss incurred by circuit blocks
during standby mode.
Power dissipation (Ptotal = Pstatic and Pdynamic) in a complementary metal-oxide
semiconductor (CMOS) circuit comes from two sources: static and dynamic. A quadratic
dependency on the dynamic switching power and a more than linear dependency on static
power as a form of gate leakage (subthreshold current) exist. To reduce dynamic power
loss, the supply power should be reduced. A significant reduction in power dissipation
occurs when portions of a microprocessor operate at a lower voltage level. This reduction
in supply voltage is achieved via voltage regulators or converters. Voltage regulators are
used to provide a stable power supply to the microprocessor. The conventional off-chip
switching voltage regulator contains a passive floating inductor, which is difficult to be
implemented inside the chip due to excessive power dissipation and parasitic effects.
Additionally, the inductor takes a very large chip area while hampering the scaling process.
These limitations make passive inductor based on-chip regulator design very unattractive
for SOC integration and multi-/many-core environments. To circumvent the challenges,
three alternative techniques based on active circuit elements to replace the passive LC filter
of the buck convertor are developed. The first inductorless on-chip switching voltage
regulator architecture is based on a cascaded 2nd order multiple feedback (MFB) low-pass
filter (LPF). This design has the ability to modulate to multiple voltage settings via pulse
with modulation (PWM). The second approach is a supplementary design utilizing a hybrid
low drop-out scheme to lower the output ripple of the switching regulator over a wider
frequency range. The third design approach allows the integration of an entire power
management system within a single chipset by combining a highly efficient switching
regulator with an intermittently efficient linear regulator (area efficient), for robust and
highly efficient on-chip regulation.
The static power (Pstatic) or subthreshold leakage power (Pleak) increases with
technology scaling. To mitigate static power dissipation, power gating techniques are
implemented. Power gating is one of the popular methods to manage leakage power during
standby periods in low-power high-speed IC design. It works by using transistor based
switches to shut down part of the circuit block and put them in the idle mode. The efficiency
of a power gating scheme involves minimum Ioff and high Ion for the sleep transistor. A
conventional sleep transistor circuit design requires an additional header, footer, or both
switches to turn off the logic block. This additional transistor causes signal delay and
increases the chip area. We propose two innovative designs for next generation sleep
transistor designs. For an above threshold operation, we present a sleep transistor design
based on fully depleted silicon-on-insulator (FDSOI) device. For a subthreshold circuit
operation, we implement a sleep transistor utilizing the newly developed silicon-on
ferroelectric-insulator field effect transistor (SOFFET). In both of the designs, the ability
to control the threshold voltage via bias voltage at the back gate makes both devices more
flexible for sleep transistors design than a bulk MOSFET. The proposed approaches
simplify the design complexity, reduce the chip area, eliminate the voltage drop by sleep
transistor, and improve power dissipation. In addition, the design provides a dynamically
controlled Vt for times when the circuit needs to be in a sleep or switching mode.Introduction -- Background and literature review -- Fully integrated on-chip switching voltage regulator -- Hybrid LDO voltage regulator based on cascaded second order multiple feedback loop -- Single and dual output two-stage on-chip power management system -- Sleep transistor design using double-gate FDSOI -- Subthreshold region sleep transistor design -- Conclusio
Ultra Low Power Circuits for Internet of Things and Deep Learning Accelerator Design with In-Memory Computing
Collecting data from environment and converting gathered data into information is the key idea of Internet of Things (IoT). Miniaturized sensing devices enable the idea for many applications including health monitoring, industrial sensing, and so on. Sensing devices typically have small form factor and thus, low battery capacity, but at the same time, require long life time for continuous monitoring and least frequent battery replacement. This thesis introduces three analog circuit design techniques featuring ultra-low power consumption for such requirements: (1) An ultra-low power resistor-less current reference circuit, (2) A 110nW resistive frequency locked on-chip oscillator as a timing reference, (3) A resonant current-mode wireless power receiver and battery charger for implantable systems.
Raw data can be efficiently transformed into useful information using deep learning. However deep learning requires tremendous amount of computation by its nature, and thus, an energy efficient deep learning hardware is highly demanded to fully utilize this algorithm in various applications. This thesis also presents a pulse-width based computation concept which utilizes in-memory computing of SRAM.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/144173/1/myungjun_1.pd
Modeling the Temperature Bias of Power Consumption for Nanometer-Scale CPUs in Application Processors
We introduce and experimentally validate a new macro-level model of the CPU
temperature/power relationship within nanometer-scale application processors or
system-on-chips. By adopting a holistic view, this model is able to take into
account many of the physical effects that occur within such systems. Together
with two algorithms described in the paper, our results can be used, for
instance by engineers designing power or thermal management units, to cancel
the temperature-induced bias on power measurements. This will help them gather
temperature-neutral power data while running multiple instance of their
benchmarks. Also power requirements and system failure rates can be decreased
by controlling the CPU's thermal behavior.
Even though it is usually assumed that the temperature/power relationship is
exponentially related, there is however a lack of publicly available physical
temperature/power measurements to back up this assumption, something our paper
corrects. Via measurements on two pertinent platforms sporting nanometer-scale
application processors, we show that the power/temperature relationship is
indeed very likely exponential over a 20{\deg}C to 85{\deg}C temperature range.
Our data suggest that, for application processors operating between 20{\deg}C
and 50{\deg}C, a quadratic model is still accurate and a linear approximation
is acceptable.Comment: Submitted to SAMOS 2014; International Conference on Embedded
Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV
Low-power switched capacitor voltage reference
Low-power analog design represents a developing technological trend as it emerges from a rather limited range of applications to a much wider arena affecting mainstream market segments. It especially affects portable electronics with respect to battery life, performance, and physical size. Meanwhile, low-power analog design enables technologies such as sensor networks and RFID. Research opportunities abound to exploit the potential of low power analog design, apply low-power to established fields, and explore new applications. The goal of this effort is to design a low-power reference circuit that delivers an accurate reference with very minimal power consumption. The circuit and device level low-power design techniques are suitable for a wide range of applications. To meet this goal, switched capacitor bandgap architecture was chosen. It is the most suitable for developing a systematic, and groundup, low-power design approach. In addition, the low-power analog cell library developed would facilitate building a more complex low-power system. A low-power switched capacitor bandgap was designed, fabricated, and fully tested. The bandgap generates a stable 0.6-V reference voltage, in both the discrete-time and continuous-time domain. The system was thoroughly tested and individual building blocks were characterized. The reference voltage is temperature stable, with less than a 100 ppm/°C drift, over a --60 dB power supply rejection, and below a 1 [Mu]A total supply current (excluding optional track-and-hold). Besides using it as a voltage reference, potential applications are also described using derivatives of this switched capacitor bandgap, specifically supply supervisory and on-chip thermal regulation
Subthreshold design of ultra low-power analog modules
Il consumo di potenza rappresenta l’indicatore chiave delle performance di recenti applicazioni portatili, come dispositivi medici impiantabili o tag RFID passivi, allo scopo di aumentare, rispettivamente, i tempi di funzionamento o i range operativi. La riduzione della tensione di alimentazione si è dimostrata l’approccio migliore per ridurre il consumo di potenza dei sistemi digitali integrati. Al fine di tenere il passo con la riduzione delle tensioni di alimentazione, anche le sezioni analogiche dei sistemi mixed signal devono essere in grado di funzionare con livelli di tensione molto bassi. Di conseguenza, sono richieste nuove metodologie di progettazione analogica e configurazioni circuitali innovative in grado di lavorare con tensioni di alimentazioni bassissime, dissipando una potenza estremamente bassa. Il regime di funzionamento sottosoglia consente di ridurre notevolmente le tensioni applicabili ai dispositivi ed si contraddistingue per i livelli di corrente molto bassi, rispetto al ben noto funzionamento in forte inversione. Queste due caratteristiche sono state sfruttate nella realizzazione di moduli analogici di base ultra low voltage, low power.
Tre nuove architetture di riferimenti di tensione, che lavorano con tutti i transistor polarizzati in regime sottosoglia, sono stati fabbricati in tecnologia CMOS 0.18 μm. I tre circuiti si basano sullo stesso principio di funzionamento per compensare gli effetti della variazione della temperatura sulla tensione di riferimento generata. Tramite il principio di funzionamento proposto, la tensione di riferimento può essere approssimata con la differenza delle tensioni di soglia, a temperatura ambiente, dei transistor. Misure sperimentali sono state effettuate su set con più di 30 campioni per ogni configurazione circuitale. Una dettagliata analisi statistica ha dimostrato un consumo medio di potenza che va da pochi nano watt a poche decine di nano watt, mentre la minima tensione di alimentazione, raggiunta da una delle tre configurazioni, è di soli 0.45 V. Le tensioni di riferimento generate sono molto precise rispetto alle variazioni della temperatura e della tensione di alimentazione, infatti sono stati ottenuti coefficienti di temperatura e line sensitivity medi a partire rispettivamente da 165 ppm/°C e 0.065 %/V.
Inoltre, è stata trattata anche la progettazione di amplificatori ultra low voltage, low power. Sono state illustrate linee guida dettagliate per la progettazione di amplificatori sottosoglia e le stesse sono state applicate per la realizzazione di un amplificatore a due stadi, con compensazione di Miller, funzionante con una tensione di alimentazione di 0.5 V. I risultati sperimentali dell’op amp proposto, fabbricato in tecnologia CMOS 0.18 μm, hanno mostrato un guadagno DC ad anello aperto di 70 dB, un prodotto banda guadagno di 18 kHz ed un consumo di potenza di soli 75 nW. I risultati delle misure sperimentali dimostrano che gli amplificatori operazionali in sottosoglia rappresentano una soluzione molto interessante nella realizzazione di applicazioni efficienti in termini energetici per gli attuali sistemi elettronici portatili. Dal confronto con amplificatori ultra low power, low voltage presenti in letteratura, si evince che la soluzione proposta offre un miglior compromesso tra velocità , potenza dissipata e capacità di carico
A novel deep submicron bulk planar sizing strategy for low energy subthreshold standard cell libraries
Engineering andPhysical Science ResearchCouncil
(EPSRC) and Arm Ltd for providing funding in the form of grants and studentshipsThis work investigates bulk planar deep submicron semiconductor physics in an attempt
to improve standard cell libraries aimed at operation in the subthreshold regime and in
Ultra Wide Dynamic Voltage Scaling schemes. The current state of research in the field is
examined, with particular emphasis on how subthreshold physical effects degrade
robustness, variability and performance. How prevalent these physical effects are in a
commercial 65nm library is then investigated by extensive modeling of a BSIM4.5
compact model. Three distinct sizing strategies emerge, cells of each strategy are laid out
and post-layout parasitically extracted models simulated to determine the
advantages/disadvantages of each. Full custom ring oscillators are designed and
manufactured. Measured results reveal a close correlation with the simulated results, with
frequency improvements of up to 2.75X/2.43X obs erved for RVT/LVT devices
respectively. The experiment provides the first silicon evidence of the improvement
capability of the Inverse Narrow Width Effect over a wide supply voltage range, as well
as a mechanism of additional temperature stability in the subthreshold regime.
A novel sizing strategy is proposed and pursued to determine whether it is able to produce
a superior complex circuit design using a commercial digital synthesis flow. Two 128 bit
AES cores are synthesized from the novel sizing strategy and compared against a third
AES core synthesized from a state-of-the-art subthreshold standard cell library used by
ARM. Results show improvements in energy-per-cycle of up to 27.3% and frequency
improvements of up to 10.25X. The novel subthreshold sizing strategy proves superior
over a temperature range of 0 °C to 85 °C with a nominal (20 °C) improvement in
energy-per-cycle of 24% and frequency improvement of 8.65X.
A comparison to prior art is then performed. Valid cases are presented where the
proposed sizing strategy would be a candidate to produce superior subthreshold circuits
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