A Very High Speed True Random Number Generator with Entropy Assessment

International audienceThe proposed true random number generator (TRNG) exploits the jitter of events propagating in a self-timed ring (STR) to generate random bit sequences at a very high bit rate. It takes advantage of a special feature of STRs that allows the time elapsed between successive events to be set as short as needed, even in the order of picoseconds. If the time interval between the events is set in concordance with the clock jitter magnitude, a simple entropy extraction scheme can be applied to generate random numbers. The proposed STR-based TRNG (STRNG) follows AIS31 recommendations: by using the proposed stochastic model, designers can compute a lower entropy bound as a function of the STR characteristics (number of stages, oscillation period and jitter magnitude). Using the resulting entropy assessment, they can then set the compression rate in the arithmetic post-processing block to reach the required security level determined by the entropy per output bit. Implementation of the generator in two FPGA families confirmed its feasibility in digital technologies and also confirmed it can provide high quality random bit sequences that pass the statistical tests required by AIS31 at rates as high as 200 Mbit/s

A Very High Speed True Random Number Generator with Entropy Assessment

International audienceThe proposed true random number generator (TRNG) exploits the jitter of events propagating in a self-timed ring (STR) to generate random bit sequences at a very high bit rate. It takes advantage of a special feature of STRs that allows the time elapsed between successive events to be set as short as needed, even in the order of picoseconds. If the time interval between the events is set in concordance with the clock jitter magnitude, a simple entropy extraction scheme can be applied to generate random numbers. The proposed STR-based TRNG (STRNG) follows AIS31 recommendations: by using the proposed stochastic model, designers can compute a lower entropy bound as a function of the STR characteristics (number of stages, oscillation period and jitter magnitude). Using the resulting entropy assessment, they can then set the compression rate in the arithmetic post-processing block to reach the required security level determined by the entropy per output bit. Implementation of the generator in two FPGA families confirmed its feasibility in digital technologies and also confirmed it can provide high quality random bit sequences that pass the statistical tests required by AIS31 at rates as high as 200 Mbit/s

On-chip jitter measurement for true random number generators

Applications of true random number generators (TRNGs) span from art to numerical computing and system security. In cryptographic applications, TRNGs are used for generating new keys, nonces and masks. For this reason, a TRNG is an essential building block and often a point of failure for embedded security systems. One type of primitives that are widely used as source of randomness are ring oscillators. For a ring-oscillator-based TRNG, the true randomness originates from its timing jitter. Therefore, determining the jitter strength is essential to estimate the quality of a TRNG. In this paper, we propose a method to measure the jitter strength of a ring oscillator implemented on an FPGA. The fast tapped delay chain is utilized to perform the on-chip measurement with a high resolution. The proposed method is implemented on both a Xilinx FPGA and an Intel FPGA. Fast carry logic components on different FPGAs are used to implement the fast delay line. This carry logic component is designed to be fast and has dedicated routing, which enables a precise measurement. The differential structure of the delay chain is used to thwart the influence of undesirable noise from the measurement. The proposed methodology can be applied to other FPGA families and ASIC designs

Stochastic Bayesian Computation for Autonomous Robot Sensorimotor System

International audienceThis paper presents a stochastic computing implementationof a Bayesian sensorimotor system that performsobstacle avoidance for an autonomous robot. In a previouswork we have shown that we are able to automatically design aprobabilistic machine which computes inferences on a Bayesianmodel using stochastic arithmetic. We start from a high levelBayesian model description, then our compiler generates anelectronic circuit, corresponding to the probabilistic inference,operating on stochastic bit streams. Our goal in this paper isto show that our compilation toolchain and simulation devicework on a classic robotic application, sensor fusion for obstacleavoidance. The novelty is in the way the computations are implemented,opening the way for future low power autonomousrobots using such circuits to perform Bayesian Inference

Image encryption framework based on multi-chaotic maps and equal pixel values quantization

Abstract The importance of image encryption has considerably increased, especially after the dramatic evolution of the internet and network communications, due to the simplicity of capturing and transferring digital images. Although there are several encryption approaches, chaos-based image encryption is considered the most appropriate approach for image applications because of its sensitivity to initial conditions and control parameters. Confusion and diffusion methods have been used in conventional image encryption methods, but the ideal encrypted image has not yet been achieved. This research aims to generate an encrypted image free of statistical information to make cryptanalysis infeasible. Additionally, the motivation behind this work lies in addressing the shortcomings of conventional image encryption methods, which have not yet achieved the ideal encrypted image. The proposed framework aims to overcome these challenges by introducing a new method, Equal Pixel Values Quantization (EPVQ), along with enhancing the confusion and diffusion processes using chaotic maps and additive white Gaussian noise. Key security, statistical properties of encrypted images, and withstanding differential attacks are the most important issues in the field of image encryption. Therefore, a new method, Equal Pixel Values Quantization (EPVQ), was introduced in this study in addition to the proposed confusion and diffusion methods to achieve an ideal image encryption framework. Generally, the confusion method uses Sensitive Logistic Map (SLM), Henon Map, and additive white Gaussian noise to generate random numbers for use in the pixel permutation method. However, the diffusion method uses the Extended Bernoulli Map (EBM), Tinkerbell, Burgers, and Ricker maps to generate the random matrix. Internal Interaction between Image Pixels (IIIP) was used to implement the XOR (Exclusive OR) operator between the random matrix and scrambled image. Basically, the EPVQ method was used to idealize the histogram and information entropy of the ciphered image. The correlation between adjacent pixels was minimized to have a very small value (×10−3). Besides, the key space was extended to be very large (2450) considering the key sensitivity to hinder brute force attacks. Finally, a histogram was idealized to be perfectly equal in all occurrences, and the resulting information entropy was equal to the ideal value (8), which means that the resulting encrypted image is free of statistical properties in terms of the histogram and information entropy. Based on the findings, the high randomness of the generated random sequences of the proposed confusion and diffusion methods is capable of producing a robust image encryption framework against all types of cryptanalysis attacks

D2.1 - Report on Selected TRNG and PUF Principles

This report represents the final version of Deliverable 2.1 of the HECTOR work package WP2. It is a result of discussions and work on Task 2.1 of all HECTOR partners involved in WP2. The aim of the Deliverable 2.1 is to select principles of random number generators (RNGs) and physical unclonable functions (PUFs) that fulfill strict technology, design and security criteria. For example, the selected RNGs must be suitable for implementation in logic devices according to the German AIS20/31 standard. Correspondingly, the selected PUFs must be suitable for applying similar security approach. A standard PUF evaluation approach does not exist, yet, but it should be proposed in the framework of the project. Selected RNGs and PUFs should be then thoroughly evaluated from the point of view of security and the most suitable principles should be implemented in logic devices, such as Field Programmable Logic Arrays (FPGAs) and Application Specific Integrated Circuits (ASICs) during the next phases of the project