A generalization of Dijkstra's shortest path algorithm with applications to VLSI routing

AbstractWe generalize Dijkstra's algorithm for finding shortest paths in digraphs with non-negative integral edge lengths. Instead of labeling individual vertices we label subgraphs which partition the given graph. We can achieve much better running times if the number of involved subgraphs is small compared to the order of the original graph and the shortest path problems restricted to these subgraphs is computationally easy.As an application we consider the VLSI routing problem, where we need to find millions of shortest paths in partial grid graphs with billions of vertices. Here, our algorithm can be applied twice, once in a coarse abstraction (where the labeled subgraphs are rectangles), and once in a detailed model (where the labeled subgraphs are intervals). Using the result of the first algorithm to speed up the second one via goal-oriented techniques leads to considerably reduced running time. We illustrate this with a state-of-the-art routing tool on leading-edge industrial chips

A Minimum Cost Path Search Algorithm Through Tile Obstacles

ABSTRACT In this paper, based on tile connection graph, we propose an efficient minimum cost path search algorithm through tile obstacles. This search algorithm is faster than previous graph based algorithm and unlike previous tile based algorithms, this algorithm finds the minimum cost path

A Density-Based General Greedy Channel Routing Algorithm in VLSI Design Automation.

One of the most important forms of routing strategies is called channel routing . This approach allows us to reduce the extremely difficult VLSI layout problem to a collection of simpler subproblems. For channel routing problems, most frequently mentioned heuristic algorithms use parameters derived from experiments to approach the routing solution without carefully considering the effect of each selected wire segment to the final routing solution. In this dissertation, we propose a new channel routing algorithm in the two-layer restricted-Manhattan routing model (2-RM) in detail. There are three phases involved in developing the new routing algorithm. In the first phase, we distinguish one type of wire from the others using some optimality criteria, which makes the selection of a set of best horizontal wire segments for a track more effective so that good performance of the generated routing solutions can be achieved. In the second phase, we develop a theoretical framework related to two major data structures, column density and vertical constraint graph, which effectively improves search efficiency and routing performance. Finally in the third phase, we develop an efficient powerful heuristic channel routing algorithm based on the concepts shown in phase one and the theoretical framework proposed in phase two. We highlight the application of our algorithm to the channel routing problems in the three-layer restricted-Manhattan overlap (3-RM-O) and three-layer Manhattan overlay (3-M-O) routing models. On many tests we have conducted on the examples known in the literature, our algorithm has performed as well or better than the existing algorithms in both 2-RM and 3-M-O routing models. Our experiments show that our approach has the potential to outperform other algorithms in other routing models

Shortest Paths and Steiner Trees in VLSI Routing

Routing is one of the major steps in very-large-scale integration (VLSI) design. Its task is to find disjoint wire connections between sets of points on a chip, subject to numerous constraints. This problem is solved in a two-stage approach, which consists of so-called global and detailed routing steps. For each set of metal components to be connected, global routing reduces the search space by computing corridors in which detailed routing sequentially determines the desired connections as shortest paths. In this thesis, we present new theoretical results on Steiner trees and shortest paths, the two main mathematical concepts in routing. In the practical part, we give computational results of BonnRoute, a VLSI routing tool developed at the Research Institute for Discrete Mathematics at the University of Bonn. Interconnect signal delays are becoming increasingly important in modern chip designs. Therefore, the length of paths or direct delay measures should be taken into account when constructing rectilinear Steiner trees. We consider the problem of finding a rectilinear Steiner minimum tree (RSMT) that --- as a secondary objective --- minimizes a signal delay related objective. Given a source we derive some structural properties of RSMTs for which the weighted sum of path lengths from the source to the other terminals is minimized. Also, we present an exact algorithm for constructing RSMTs with weighted sum of path lengths as secondary objective, and a heuristic for various secondary objectives. Computational results for industrial designs are presented. We further consider the problem of finding a shortest rectilinear Steiner tree in the plane in the presence of rectilinear obstacles. The Steiner tree is allowed to run over obstacles; however, if it intersects an obstacle, then no connected component of the induced subtree must be longer than a given fixed length. This kind of length restriction is motivated by its application in VLSI routing where a large Steiner tree requires the insertion of repeaters which must not be placed on top of obstacles. We show that there are optimal length-restricted Steiner trees with a special structure. In particular, we prove that a certain graph (called augmented Hanan grid) always contains an optimal solution. Based on this structural result, we give an approximation scheme for the special case that all obstacles are of rectangular shape or are represented by at most a constant number of edges. Turning to the shortest paths problem, we present a new generic framework for Dijkstra's algorithm for finding shortest paths in digraphs with non-negative integral edge lengths. Instead of labeling individual vertices, we label subgraphs which partition the given graph. Much better running times can be achieved if the number of involved subgraphs is small compared to the order of the original graph and the shortest path problems restricted to these subgraphs is computationally easy. As an application we consider the VLSI routing problem, where we need to find millions of shortest paths in partial grid graphs with billions of vertices. Here, the algorithm can be applied twice, once in a coarse abstraction (where the labeled subgraphs are rectangles), and once in a detailed model (where the labeled subgraphs are intervals). Using the result of the first algorithm to speed up the second one via goal-oriented techniques leads to considerably reduced running time. We illustrate this with the routing program BonnRoute on leading-edge industrial chips. Finally, we present computational results of BonnRoute obtained on real-world VLSI chips. BonnRoute fulfills all requirements of modern VLSI routing and has been used by IBM and its customers over many years to produce more than one thousand different chips. To demonstrate the strength of BonnRoute as a state-of-the-art industrial routing tool, we show that it performs excellently on all traditional quality measures such as wire length and number of vias, but also on further criteria of equal importance in the every-day work of the designer

ハイセン モンダイ ノ ヘイレツ ショリ ホウシキ ニ カンスル ケンキュウ

本論文は，プリント基板やVLSI内部の配線問題の並列処理に関する研究の成 果をまとめたものであり，次の6章から構成される. 第1章では，プリント基板やVLSI内部の配線問題の発達の歴史的背景と，本 研究を行うに至った直接の背景について述べると共に，本研究の目的と得られ た諸成果の概略を述べる. 第2章では，プリント基板やVLSI内部の配線問題とその逐次解法について述 べ，歴史的な2つの並列化方式とその問題点について述べる.そして並列計算 機のアーキテクチャを概説し，専用並列計算機と汎用並列計算機による並列配 線方式と配線処理の現状について述べる. 第3章では，計算機アーキテクチャに対して依存性を抑えるために，アーキ テクチャ固有の機能を使用せず，並列計算機が本来持っている基本的な機能 (プロセッサ間通信)のみを用いて構成されるプロセッサ競合方式による並列 配線処理方式を提案する.これは，計算モデルにマスタ・スレーブモデルを用 いて計算機アーキテクチャに対する依存性を抑え，かつ計算粒度の粗い並列処 理において高い並列性を得るための方式である.この方式を分散メモリ型並列 計算機と共有メモリ型並列計算機においてそれぞれ評価した結果，分散メモリ 型では63台のプロセッサにより約30倍の高速化を実現し，共有メモリ型で は7台のプロセッサにおいて約7倍の高速化を実現した.また，両方式の比較 検証を行ったことについて述べる. 第4章では，プロセッサ競合方式で問題であった配線品質に関する解決方法 として，引き剥し再配線処理の反復による経路改善を並列に実行する並列経路 改善方式を提案する.これはプロセッサ競合方式を基本モデルに用いて複数の 配線経路の引き剥し再配線処理を同時に行うものである. この方法では，配線 コストを用いた経路探索法により配線経路間の交差・接触を許容し，ペナルティ を用いた評価により配線順序に対する依存性を抑える.本方式をMIMD型並列 計算機により評価した結果，配線品質の改善が確認されたことについて述べる. 第5章では，多端子ネットの配線問題において並列経路改善方式を適用し， 部分引き剥し再配線のための経路探索法を提案する.これは多端子ネットの経 路探索が複数の部分的な経路探索から構成されることに着目し，この部分的な 探索単位による並列処理によりプロセッサへの処理の動的割り当て，及びネッ ト内の並列性とネット間の並列性を用いた2段階の高度な並列処理を可能にす る.更に，引き剥し再配線による経路改善において，配線経路を部分的に引き 剥すことにより経路改善のための再配線回数を削減する.本方式を逐次プログ ラムで評価した結果，経路改善において探索回数の削減と，配線結果が収束す るまでの経路改善回数の削減が確認されたので，これらの詳細と並列処理への 適合性，及び動的処理割り当てと並列性抽出の方針についての考察について述 べる. 第6章は結論であり，本研究で得られた諸結果を総括的に述べると共に，今 後の課題について述べる

A Tile-Expansion Router

A router based on a tile-expansion algorithm and corner stitching data structure is presented. This program finds connections with a minimum number of jogs and it ensures that a possible solution will be found. Using a working tree, it allows an exhaustive and recursive search along all available areas for routing. The connections are made going back through the working tree until the starting terminal is reached. There are two Manhattan layers that the user can choose for each direction to implement connections; the router can be used to wire hierarchical blocks using a chip planning methodology. The program has been successfully tested on examples concerning different classes of problems