A statistical bit error generator for emulation of complex forward error correction schemes

Forward error correction (FEC schemes are generally used in wireless communication systems to maintain an acceptable quality of service. Various models have been proposed in literature to predict the end-to-end quality of wireless video systems. However, most of these models utilize simplistic error generators which do not accurately represent any practical wireless channel. A more accurate way is to evaluate the quality of a video system using Monte Carlo techniques. However these necessitate huge computational times, making these methods unpractical. This paper proposes an alternative method that can be used in modeling of complex communications systems with minimal computational time. The proposed three random variable method was used to model two FEC schemes adopted by the digital video broadcasting (DVB) standard. Simulation results confirm that this method closely matches the performance of the considered communication systems in both bit error rate (BER) and peak signal-to-noise ratio (PSNR).peer-reviewe

A generic radio channel emulator to evaluate higher layer protocols in a CDMA system

Currently, we are involved in the standardisation process to specify the next mobile system generation. A wideband code division multiple access (WCDMA) system is considered in most of the region versions. It would be very useful to count on a radio channel emulator which allows one to evaluate higher layers protocols within this context. This paper presents a radio channel emulator developed for a code division multiple access (CDMA) based system. Its versatility and low complexity have been exposed, and the validation process to check the model accuracy has also been shown for this system as an example.Peer ReviewedPostprint (published version

Accurate modelling of Ka-band videoconferencing systems based on the quality of experience

This work formed part of the project TWISTER, which was financially supported under the European Union 6th Framework Programme (FP6). The authors are solely responsible for the contents of the paper, which does not represent the opinion of the European Commission.Ka-band satellite multimedia communication networks play important roles because of their capability to provide the required bandwidth in remote places of the globe. However, because of design complexity, in practice they suffer from poor design and performance degradation because of being practically forced to guarantee acceptable end-user satisfaction in conditions of extremely low bit error rates, which is emphasised with the vulnerability of compressed video content to transmission errors, often impossible to be applied during the service development phase. A novel discrete event simulation model is presented, which provides performance estimation for such systems based on subjective measurement and a better quality of experience. The authors show that the proposed model reduces implementation cost and is flexible to be used for different network topologies around the globe.peer-reviewe

Improve the Usability of Polar Codes: Code Construction, Performance Enhancement and Configurable Hardware

Error-correcting codes (ECC) have been widely used for forward error correction (FEC) in modern communication systems to dramatically reduce the signal-to-noise ratio (SNR) needed to achieve a given bit error rate (BER). Newly invented polar codes have attracted much interest because of their capacity-achieving potential, efficient encoder and decoder implementation, and flexible architecture design space.This dissertation is aimed at improving the usability of polar codes by providing a practical code design method, new approaches to improve the performance of polar code, and a configurable hardware design that adapts to various specifications. State-of-the-art polar codes are used to achieve extremely low error rates. In this work, high-performance FPGA is used in prototyping polar decoders to catch rare-case errors for error-correcting performance verification and error analysis. To discover the polarization characteristics and error patterns of polar codes, an FPGA emulation platform for belief-propagation (BP) decoding is built by a semi-automated construction flow. The FPGA-based emulation achieves significant speedup in large-scale experiments involving trillions of data frames. The platform is a key enabler of this work. The frozen set selection of polar codes, known as bit selection, is critical to the error-correcting performance of polar codes. A simulation-based in-order bit selection method is developed to evaluate the error rate of each bit using Monte Carlo simulations. The frozen set is selected based on the bit reliability ranking. The resulting code construction exhibits up to 1 dB coding gain with respect to the conventional bit selection. To further improve the coding gain of BP decoder for low-error-rate applications, the decoding error mechanisms are studied and analyzed, and the errors are classified based on their distinct signatures. Error detection is enabled by low-cost CRC concatenation, and post-processing algorithms targeting at each type of the error is designed to mitigate the vast majority of the decoding errors. The post-processor incurs only a small implementation overhead, but it provides more than an order of magnitude improvement of the error-correcting performance. The regularity of the BP decoder structure offers many hardware architecture choices. Silicon area, power consumption, throughput and latency can be traded to reach the optimal design points for practical use cases. A comprehensive design space exploration reveals several practical architectures at different design points. The scalability of each architecture is also evaluated based on the implementation candidates. For dynamic communication channels, such as wireless channels in the upcoming 5G applications, multiple codes of different lengths and code rates are needed to t varying channel conditions. To minimize implementation cost, a universal decoder architecture is proposed to support multiple codes through hardware reuse. A 40nm length- and rate-configurable polar decoder ASIC is demonstrated to fit various communication environments and service requirements.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/140817/1/shuangsh_1.pd

Functional and timing implications of transient faults in critical systems

Embedded systems in critical domains, such as auto-motive, aviation, space domains, are often required to guarantee both functional and temporal correctness. Considering transient faults, fault analysis and mitigation approaches are implemented at various levels of the system design, in order to maintain the functional correctness. However, transient faults and their mitigation methods have a timing impact, which can affect the temporal correctness of the system. In this work, we expose the functional and the timing implications of transient faults for critical systems. More precisely, we initially highlight the timing effect of transient faults occurring in the combinational and sequential logic of a processor. Furthermore, we propose a full stack vulnerability analysis that drives the design of selective hardware-based mitigation for real-time applications. Last, we study the timing impact of software-based reliability mitigation methods applied in a COTS GPU, using a fault tolerant middleware.This work has been partially funded by ANR-FASY (ANR-21-CE25-0008-01) and received funding by ESA through the 4000136514/21/NL/GLC/my co-funded PhD activity ”Mixed Software/Hardware-based Fault-tolerance Techniques for Complex COTS System-on-Chip in Radiation Environments” and the GPU4S (GPU for Space) project. Moreover, it was partially supported by the Spanish Ministry of Economy and Competitiveness under grants PID2019-107255GB-C21 and IJC2020-045931-I (Spanish State Research Agency / http://dx.doi.org/10.13039/501100011033), by the European Union’s Horizon 2020 grant agreement No 739551 (KIOS CoE) and from the Government of the Republic of Cyprus through the Cyprus Deputy Ministry of Research, Innovation and Digital Policy.Peer ReviewedPostprint (author's final draft

Digital implementation of an upstream DOCSIS QAM modulator and channel emulator

The concept of cable television, originally called community antenna television (CATV), began in the 1940's. The information and services provided by cable operators have changed drastically since the early days. Cable service providers are no longer simply providing their customers with broadcast television but are providing a multi-purpose, two-way link to the digital world. Custom programming, telephone service, radio, and high-speed internet access are just a few of the services offered by cable service providers in the 21st century. At the dawn of the internet the dominant mode of access was through telephone lines. Despite advances in dial-up modem technology, the telephone system was unable to keep pace with the demand for data throughput. In the late 1990's an industry consortium known as Cable Television Laboratories, Inc. developed a standard protocol for providing high-speed internet access through the existing CATV infrastructure. This protocol is known as Data Over Cable Service Interface Specification (DOCSIS) and it helped to usher in the era of the information superhighway. CATV systems use different parts of the radio frequency (RF) spectrum for communication to and from the user. The downstream portion (data destined for the user) consumes the bulk of the spectrum and is located at relatively high frequencies. The upstream portion (data destined to the network from the user) of the spectrum is smaller and located at the low end of the spectrum. This lower frequency region of the RF spectrum is particularly prone to impairments such as micro-reflections, which can be viewed as a type of multipath interference. Upstream data transfer in the presence of these impairments is therefore problematic and requires complex signal correction algorithms to be employed in the receiver. The quality of a receiver is largely determined by how well it mitigates the signal impairments introduced by the channel. For this reason, engineers developing a receiver require a piece of equipment that can emulate the channel impairments in any permutation in order to test their receiver. The conventional test methodology uses a hardware RF channel emulator connected between the transmitter and the receiver under test. This method not only requires an expensive RF channel emulator, but a functioning analog front-end as well. Of these two problems, the expense of the hardware emulator is likely less important than the delay in development caused by waiting for a functional analog front-end. Receiver design is an iterative, time consuming process that requires the receiver's digital signal processing (DSP) algorithms be tested as early as possible to reduce the time-to-market. This thesis presents a digital implementation of a DOCSIS-compliant channel emulator whereby cable micro-reflections and thermal noise at the analog front-end of the receiver are modelled digitally at baseband. The channel emulator and the modulator are integrated into a single hardware structure to produce a compact circuit that, during receiver testing, resides inside the same field programmable gate array (FPGA) as the receiver. This approach removes the dependence on the analog front-end allowing it to be developed concurrently with the receiver's DSP circuits, thus reducing the time-to-market. The approach taken in this thesis produces a fully programmable channel emulator that can be loaded onto FPGAs as needed by engineers working independently on different receiver designs. The channel emulator uses 3 independent data streams to produce a 3-channel signal, whereby a main channel with micro-reflections is flanked on either side by adjacent channels. Thermal noise normally generated by the receiver's analog front-end is emulated and injected into the signal. The resulting structure utilizes 43 dedicated multipliers and 401.125 KB of RAM, and achieves a modulation error ratio (MER) of 55.29 dB

Enhancing error resilience in wireless transmitted compressed video sequences through a probabilistic neural network core

Video compression standards commonly employed in the delivery of real-time wireless multimedia services regularly adopt variable length codes (VLCs) for efficient transmission. This coding technique achieves the necessary high compression ratios at the expense of an increased system’s vulnerability to transmission errors. The more frequent presence of transmission errors in wireless channels requires video compression standards to accurately detect, localize and conceal any corrupted macroblocks (MBs) present in the video sequence. Unfortunately, standard decoders offer limited error detection and localization capabilities posing a bound on the perceived video quality of the reconstructed video sequence. This paper presents a novel solution which enhances the error detection and localization capabilities of standard decoders through the application of a Probabilistic Neural Network (PNN). The proposed solution generally outperforms other error detection mechanisms present in literature, as it manages to improve the standard decoder’s error detection rate by up to 95.74%. Index Terms — Error detection coding, learning systems, multimedia communications, video coding, wireless networks.peer-reviewe