High Efficiency IGBTs through Novel Three-Dimensional Modelling and New Architectures

New Insulated Gate Bipolar Transistor (IGBT) designs are reliant on simulation tools, such as Sentaurus technology computer-aided design (TCAD) models, which allow for rapid device development that could not be achieved by manufacturing prototypes due to the cost and time associated with fabrication. These simulations are, though, computationally expensive and typically most design engineers develop these TCAD models only in two dimensions. This leads to inaccuracies in the model output since manufactured transistors are inherently three-dimensional (3D). Based upon a commercial IGBT, this thesis begins by outlining the development of a 3D TCAD model using design details provided by the manufacturer. Large variations between the experimental data from the manufactured device and the simulation model lead to the discovery of widespread birds-beaking within the IGBT – an uncontrollable processing defect that the manufacturer was unaware of. This thesis presents a new simulation technique to account for this processing error while minimising computational effort and investigates the consequence of this birds-beak on the reliability of the device. The verified 3D IGBT model was also used to determine an optimum cell design that considered critical 3D effects omitted from previous studies. An extensive literature review for the Reverse-Conducting IGBT (RC-IGBT) is provided. It is shown that despite the benefits of the RC-IGBT, the device suffers from many undesirable design trade-offs that have prevented its widespread use. The RC-IGBT designs that have currently been proposed in literature, either present a trade-off in performance, an inability to be manufactured, or a requirement for a custom gate drive. This thesis presents a new RC-IGBT concept, the ‘Dual Implant SuperJunction (SJ) RC-IGBT’ that addresses these concerns and is manufacturable using current state of the art techniques. The concept and proposed manufacturing method enables, for the first time, a full SuperJunction structure to be achieved in a 1.2kV device. In addition, an investigation into a coordinated switching scheme using both a silicon IGBT and silicon-carbide MOSFET was undertaken, which aimed to improve turn-off losses within the IGBT without sacrificing on-state losses. Thermal modelling of the power devices switching under inductive load was explored as the system was optimised to use a SiC MOSFET in excess of its nominal ratings, reducing the overall system cost.EPSRC Doctoral Training Partnership scheme (grant RG75686

THE CURRENT STATUS OF POWER SEMICONDUCTORS

Trends in the design and technology of power semiconductor devices are discussed on the threshold of the year 2015. Well established silicon technologies continue to occupy the most of applications thanks to the maturity of switches like MOSFET, IGBT, IGCT and PCT. Silicon carbide (SiC) and gallium nitride (GaN) are striving to take over that of the silicon. The most relevant SiC device is the MPS (JBS) diode, followed by MOSFET and JFET. GaN devices are represented by lateral HEMT. While the long term reliability of silicon devices is well trusted, the SiC MOSFETs and GaN HEMTs are struggling to achieve a similar confidence. Two order higher cost of SiC equivalent functional performance at device level limits their application to specific cases, but their number is growing. Next five years will therefore see the co-existence of these technologies. Silicon will continue to occupy the most of applications and dominate the high-power sector. The wide bandgap devices will expand mainly in the 600 - 1200 V range and dominate the research regardless of the voltage class

ADVANCED TERMINATION STRUCTURES FOR HV POWER SEMICONDUCTOR DEVICES

Thesis is in the field of power electronic devices. They operate in power conversion system as power switches able to impose the ON/OFF condition. A power device present two macroscopic areas: 1) active area; 2) termination area. The first one is responsible of conduction during the On-state of the device; while the second one mainly contributes to withstand the voltage rate during the Off-state condition. The actual trend of power devices tends to a technological scaling to increase the switching frequency and reduce the costs. As consequence, the percentage of the die area occupied by the termination is even more growing since its dimension is related to the voltage rate. This introduce the necessity to develop new termination design able to sustain the same voltage rate with a reduced consumption of area. At the same time, the new designs must also guarantee the required standard in term of reliability and ruggedness consolidated in classical designs. The scaling has also effects on the active area, where current density is even more growing leading to reliability problem from the thermal point of view. The design of new termination structure, as well as, reliability analysis of the active area have been the main focus of my third year research activities. Two new termination structure have been designed by means of 2D TCAD simulations. The new design realize an improvement of the classical Junction Termination Extension (JTE) technique to sustain a voltage rate of 1.2 kV. JTE design offers the possibility to considerably reduce the occupation of area but present great limitations in term of reliability. JTE needs of optimizing a low-doped P-region to maximize the breakdown voltage of the device. The critical point is that the breakdown voltage is strongly affected by the doping profile of the low-doped region. The breakdown stability is guaranteed only around the optimal value of the doping concentration. A deviation from the optimal value of about 7-8% already produces an inacceptable degradation of the breakdown capability. Since technological process can be subjected to fluctuation or/and contamination of external impurity able to modify the doping profile have led the JTE design to be less attractive for industry. In my activity two innovative two innovative JTE-based terminations have been presented providing a well precise optimization methodology to maximize the breakdown voltage. Both designs have been developed in order to increase the reliability of the device guaranteeing the breakdown stability in a wide range of doping concentration of the low-doped P-region. The first one design exploits the action of a special passivation layer named SIPOS; while the second one is made combining both JTE and a classical Floating Filed Ring technique. The performances of both terminations are than compared with that an advanced Floating Field Ring structure appropriately optimized. Termination ruggedness has been evaluated by means of Unclamped Inductive Switching simulations as the capacitance of power absorption until the failure event. Therefore, current crowding phenomena occurring in avalanche condition are deeply analyzed together with its relation with the Negative Differential Resistance branch on the I-V avalanche curve. During the third year I spent three months period to the Franhoufer Institute (ISIT). My research was focused on aspects regarding technological process of power devices. During this period I realized an emulation process flow of a Floating Field Ring termination for a 600V Punch-Through IGBT. The reliability of the active area was analyzed by means of Short-Circuit test. It is an industrial test able to evaluate the capacitance of power absorption during the Short-Circuit condition of a device. During the Short-Circuit, the device is driven in conduction at high voltage and the current is limited only by the internal resistance. The influence of design parameters on the Short-Circuit capability of a FS-IGBT device has been analyzed. A commercial device has been experimentally characterized by means of static curves tracker, Inductive Load Switching test and Short-Circuit test. The Short-Circuit capability analysis was led with a simulation approach by means of 3D TCAD electro-thermal simulations. The physical models of the elementary cell of the IGBT device have been calibrated to fit the characteristics of the commercial device at different temperatures. An innovative design has been proposed to increase the Short-Circuit capabilit

Composite power semiconductor switches for high-power applications

It is predicted that 80 % of the world’s electricity will flow through power electronic based converters by 2030, with a growing demand for renewable technolo gies and the highest levels of efficiency at every stage from generation to load. At the heart of a power electronic converter is the power semiconductor switch which is responsible for controlling and modulating the flow of power from the input to the output. The requirements for these power semiconductor switches are vast, and include: having an extremely low level of conduction and switching losses; being a low source of electromagnetic noise, and not being susceptible to external Electromagnetic Interference (EMI); and having a good level of ruggedness and reliability. These high-performance switches must also be economically viable and not have an unnecessarily large manufacturing related carbon footprint. This thesis investigates the switching performance of the two main semiconductor switches used in high-power applications — the well-established Silicon (Si)-Insulated-Gate Bipolar Transistor (IGBT) and the state-of-the-art Wide-Bandgap (WBG) Silicon-Carbide (SiC)-Metal–Oxide–Semiconductor Field-Effect Transistor (MOSFET). The SiC-MOSFET is ostensibly a better device than the Si-IGBT due to the lower level of losses, however the cost of the device is far greater and there are characteristics which can be troublesome, such as the high levels of oscillatory behaviour at the switching edges which can cause serious Electromagnetic Compatibility (EMC) issues. The operating mechanism of these devices, the materials which are used to make them, and their auxiliary components are critically analysed and discussed. This includes a head-to-head comparison of the two high-capacity devices in terms of their losses and switching characteristics. The design of a high-power Double-Pulse Test Rig (DPTR) and the associated high-bandwidth measurement platform is presented. This test rig is then extensively used throughout this thesis to experimentally characterise the switching performance of the aforementioned high-capacity power semiconductor devices. A hybrid switch concept — termed “The Diverter” — is investigated, with the motivation of achieving improved switching performance without the high-cost of a full SiC solution. This comprises a fully rated Si-IGBT as the main conduction device and a part-rated SiC-MOSFET which is used at the turn-off. The coordinated switching scheme for the Si/SiC-Diverter is experimentally examined to determine the required timings which yield the lowest turn-off loss and the lowest level of oscillatory behaviour and other EMI precursors. The thermal stress imposed on the part-rated SiC-MOSFET is considered in a junction temperature simulation and determined to be negligible. This concept is then analysed in a grid-tied converter simulation and compared to a fully rated SiC-MOSFET and Si-IGBT. A conduction assistance operating mode, which solely uses the part-rated SiC-MOSFET when within its rating, is also investigated. Results show that the Diverter achieves a significantly lower level of losses compared to a Si-IGBT and only marginally higher than a full SiC solution. This is achieved at a much lower cost than a full SiC solution and may also provide a better method of achieving high-current SiC switche