Circuit Design Techniques For Wideband Phased Arrays

University of Minnesota Ph.D. dissertation.June 2015. Major: Electrical Engineering. Advisor: Ramesh Harjani. 1 computer file (PDF); xii, 143 pages.This dissertation focuses on beam steering in wideband phased arrays and phase noise modeling in injection locked oscillators. Two different solutions, one in frequency and one in time, have been proposed to minimize beam squinting in phased arrays. Additionally, a differential current reuse frequency doubler for area and power savings has been proposed. Silicon measurement results are provided for the frequency domain solution (IBM 65nm RF CMOS), injection locked oscillator model verification (IBM 130nm RF-CMOS) and frequency doubler (IBM 65nm RF CMOS), while post extraction simulation results are provided for the time domain phased array solution (the chip is currently under fabrication, TSMC 65nm RF CMOS). In the frequency domain solution, a 4-point passive analog FFT based frequency tunable filter is used to channelize an incoming wideband signal into multiple narrowband signals, which are then processed through independent phase shifters. A two channel prototype has been developed at 8GHz RF frequency. Three discrete phase shifts (0 & +/- 90 degrees) are implemented through differential I-Q swapping with appropriate polarity. A minimum null-depth of 19dB while a maximum null-depth of 27dB is measured. In the time domain solution, a discrete time approach is undertaken with signals getting sampled in order of their arrival times. A two-channel prototype for a 2GHz instantaneous RF bandwidth (7GHz-9GHz) has been designed. A QVCO generates quadrature LO signals at 8GHz which are phase shifted through a 5-bit (2 extra bits from differential I-Q swapping with appropriate polarity) cartesian combiner. Baseband sampling clocks are generated from phase shifted LOs through a CMOS divide by 4 with independent resets. The design achieves an average time delay of 4.53ps with 31.5mW of power consumption (per channel, buffers excluded). An injection locked oscillator has been analyzed in s-domain using Paciorek's time domain transient equations. The simplified analysis leads to a phase noise model identical to that of a type-I PLL. The model is equally applicable to injection locked dividers and multipliers and has been extended to cover all injection locking scenarios. The model has been verified against a discrete 57MHz Colpitt's ILO, a 6.5GHz ILFD and a 24GHz ILFM with excellent matching between the model and measurements. Additionally, a differential current reuse frequency doubler, for frequency outputs between 7GHz to 14GHz, design has been developed to reduce passive area and dc power dissipation. A 3-bit capacitive tuning along with a tail current source is used to better conversion efficiency. The doubler shows FOM$_{T}$ values between 191dBc/Hz to 209dBc/Hz when driven by a 0.7GHz to 5.8GHz wide tuning VCO with a phase noise that ranges from -114dBc/Hz to -112dBc/Hz over the same bandwidth

Advanced CMOS Integrated Circuit Design and Application

The recent development of various application systems and platforms, such as 5G, B5G, 6G, and IoT, is based on the advancement of CMOS integrated circuit (IC) technology that enables them to implement high-performance chipsets. In addition to development in the traditional fields of analog and digital integrated circuits, the development of CMOS IC design and application in high-power and high-frequency operations, which was previously thought to be possible only with compound semiconductor technology, is a core technology that drives rapid industrial development. This book aims to highlight advances in all aspects of CMOS integrated circuit design and applications without discriminating between different operating frequencies, output powers, and the analog/digital domains. Specific topics in the book include: Next-generation CMOS circuit design and application; CMOS RF/microwave/millimeter-wave/terahertz-wave integrated circuits and systems; CMOS integrated circuits specially used for wireless or wired systems and applications such as converters, sensors, interfaces, frequency synthesizers/generators/rectifiers, and so on; Algorithm and signal-processing methods to improve the performance of CMOS circuits and systems

Circuits and Systems for On-Chip RF Chemical Sensors and RF FDD Duplexers

Integrating RF bio-chemical sensors and RF duplexers helps to reduce cost and area in the current applications. Furthermore, new applications can exist based on the large scale integration of these crucial blocks. This dissertation addresses the integration of RF bio-chemical sensors and RF duplexers by proposing these initiatives. A low power integrated LC-oscillator-based broadband dielectric spectroscopy (BDS) system is presented. The real relative permittivity ε’r is measured as a shift in the oscillator frequency using an on-chip frequency-to-digital converter (FDC). The imaginary relative permittivity ε”r increases the losses of the oscillator tank which mandates a higher dc biasing current to preserve the same oscillation amplitude. An amplitude-locked loop (ALL) is used to fix the amplitude and linearize the relation between the oscillator bias current and ε”r. The proposed BDS system employs a sensing oscillator and a reference oscillator where correlated double sampling (CDS) is used to mitigate the impact of flicker noise, temperature variations and frequency drifts. A prototype is implemented in 0.18 µm CMOS process with total chip area of 6.24 mm^2 to operate in 1-6 GHz range using three dual bands LC oscillators. The achieved standard deviation in the air is 2.1 ppm for frequency reading and 110 ppm for current reading. A tunable integrated electrical balanced duplexer (EBD) is presented as a compact alternative to multiple bulky SAW and BAW duplexers in 3G/4G cellular transceivers. A balancing network creates a replica of the transmitter signal for cancellation at the input of a single-ended low noise amplifier (LNA) to isolate the receive path from the transmitter. The proposed passive EBD is based on a cross-connected transformer topology without the need of any extra balun at the antenna side. The duplexer achieves around 50 dB TX-RX isolation within 1.6-2.2 GHz range up to 22 dBm. The cascaded noise figure of the duplexer and LNA is 6.5 dB, and TX insertion loss (TXIL) of the duplexer is about 3.2 dB. The duplexer and LNA are implemented in 0.18 µm CMOS process and occupy an active area of 0.35 mm^2

An Energy-Efficient Reconfigurable Mobile Memory Interface for Computing Systems

The critical need for higher power efficiency and bandwidth transceiver design has significantly increased as mobile devices, such as smart phones, laptops, tablets, and ultra-portable personal digital assistants continue to be constructed using heterogeneous intellectual properties such as central processing units (CPUs), graphics processing units (GPUs), digital signal processors, dynamic random-access memories (DRAMs), sensors, and graphics/image processing units and to have enhanced graphic computing and video processing capabilities. However, the current mobile interface technologies which support CPU to memory communication (e.g. baseband-only signaling) have critical limitations, particularly super-linear energy consumption, limited bandwidth, and non-reconfigurable data access. As a consequence, there is a critical need to improve both energy efficiency and bandwidth for future mobile devices.;The primary goal of this study is to design an energy-efficient reconfigurable mobile memory interface for mobile computing systems in order to dramatically enhance the circuit and system bandwidth and power efficiency. The proposed energy efficient mobile memory interface which utilizes an advanced base-band (BB) signaling and a RF-band signaling is capable of simultaneous bi-directional communication and reconfigurable data access. It also increases power efficiency and bandwidth between mobile CPUs and memory subsystems on a single-ended shared transmission line. Moreover, due to multiple data communication on a single-ended shared transmission line, the number of transmission lines between mobile CPU and memories is considerably reduced, resulting in significant technological innovations, (e.g. more compact devices and low cost packaging to mobile communication interface) and establishing the principles and feasibility of technologies for future mobile system applications. The operation and performance of the proposed transceiver are analyzed and its circuit implementation is discussed in details. A chip prototype of the transceiver was implemented in a 65nm CMOS process technology. In the measurement, the transceiver exhibits higher aggregate data throughput and better energy efficiency compared to prior works

Integrated RF oscillators and LO signal generation circuits

This thesis deals with fully integrated LC oscillators and local oscillator (LO) signal generation circuits. In communication systems a good-quality LO signal for up- and down-conversion in transmitters is needed. The LO signal needs to span the required frequency range and have good frequency stability and low phase noise. Furthermore, most modern systems require accurate quadrature (IQ) LO signals. This thesis tackles these challenges by presenting a detailed study of LC oscillators, monolithic elements for good-quality LC resonators, and circuits for IQ-signal generation and for frequency conversion, as well as many experimental circuits. Monolithic coils and variable capacitors are essential, and this thesis deals with good structures of these devices and their proper modeling. As experimental test devices, over forty monolithic inductors and thirty varactors have been implemented, measured and modeled. Actively synthesized reactive elements were studied as replacements for these passive devices. At first glance these circuits show promising characteristics, but closer noise and nonlinearity analysis reveals that these circuits suffer from high noise levels and a small dynamic range. Nine circuit implementations with various actively synthesized variable capacitors were done. Quadrature signal generation can be performed with three different methods, and these are analyzed in the thesis. Frequency conversion circuits are used for alleviating coupling problems or to expand the number of frequency bands covered. The thesis includes an analysis of single-sideband mixing, frequency dividers, and frequency multipliers, which are used to perform the four basic arithmetical operations for the frequency tone. Two design cases are presented. The first one is a single-sideband mixing method for the generation of WiMedia UWB LO-signals, and the second one is a frequency conversion unit for a digital period synthesizer. The last part of the thesis presents five research projects. In the first one a temperature-compensated GaAs MESFET VCO was developed. The second one deals with circuit and device development for an experimental-level BiCMOS process. A cable-modem RF tuner IC using a SiGe process was developed in the third project, and a CMOS flip-chip VCO module in the fourth one. Finally, two frequency synthesizers for UWB radios are presented

Design of a Dual Band Local Positioning System

This work presents a robust dual band local positioning system (LPS) working in the 2.4GHz and 5.8GHz industrial science medical (ISM) bands. Position measurement is based on the frequency-modulated continuous wave (FMCW) radar approach, which uses radio frequency (RF) chirp signals for propagation time and therefore distance measurements. Contrary to state of the art LPS, the presented system uses data from both bands to improve accuracy, precision and robustness. A complete system prototype is designed consisting of base stations and tags encapsulating most of the RF and analogue signal processing in custom integrated circuits. This design approach allows to reduce size and power consumption compared to a hybrid system using off-the-shelf components. Key components are implemented using concepts, which support operation in multiple frequency bands, namely, the receiver consisting of a low noise amplifier (LNA), mixer, frequency synthesizer with a wide band voltage-controlled oscillator (VCO) having broadband chirp generation capabilities and a dual band power amplifier. System imperfections occurring in FMCW radar systems are modelled. Effects neglected in literature such as compression, intermodulation, the influence of automatic gain control, blockers and spurious emissions are modeled. The results are used to derive a specification set for the circuit design. Position estimation from measured distances is done using an enhanced version of the grid search algorithm, which makes use of data from multiple frequency bands. The algorithm is designed to be easily and efficiently implemented in embedded systems. Measurements show a coverage range of the system of at least 245m. Ranging accuracy in an outdoor scenario can be as low as 8.2cm. Comparative dual band position measurements prove an effective outlier filtering in indoor and outdoor scenarios compared to single band results, yielding in a large gain of accuracy. Positioning accuracy in an indoor scenario with an area of 276m² can be improved from 1.27m at 2.4GHz and 1.86m at 5.8GHz to only 0.38m in the dual band case, corresponding to an improvement by at least a factor of 3.3. In a large outdoor scenario of 4.8 km², accuracy improves from 1.88m at 2.4GHz and 5.93m at 5.8GHz to 0.68m with dual band processing, which is a factor of at least 2.8.Die vorliegende Arbeit befasst sich mit dem Entwurf eines robusten lokalen Positionierungssystems (LPS), welches in den lizenzfreien Frequenzbereichen für industrielle, wissenschaftliche und medizinische Zwecke (industrial, scientific, medical, ISM) bei 2,4GHz und 5,8GHz arbeitet. Die Positionsbestimmung beruht auf dem Prinzip des frequenzmodulierten Dauerstrichradars (frequency modulated continuous wave, FMCW-Radar), welches hochfrequente Rampensignale für Laufzeitmessungen und damit Abstandsmessungen benutzt. Im Gegensatz zu aktuellen Arbeiten auf diesem Gebiet benutzt das vorgestellte System Daten aus beiden Frequenzbändern zur Erhöhung der Genauigkeit und Präzision sowie Verbesserung der Robustheit. Ein Prototyp des kompletten Systems bestehend aus Basisstationen und mobilen Stationen wurde entworfen. Fast die gesamte analoge hochfrequente Signalverarbeitungskette wurde als anwendungsspezifische integrierte Schaltung realisiert. Verglichen mit Systemen aus Standardkomponenten erlaubt dieser Ansatz die Miniaturisierung der Systemkomponenten und die Einsparung von Leistung. Schlüsselkomponenten wurden mit Konzepten für mehrbandige oder breitbandige Schaltungen entworfen. Dabei wurden Sender und Empfänger bestehend aus rauscharmem Verstärker, Mischer und Frequenzsynthesizer mit breitbandiger Frequenzrampenfunktion implementiert. Außerdem wurde ein Leistungsverstärker für die gleichzeitige Nutzung der beiden definierten Frequenzbänder entworfen. Um Spezifikationen für den Schaltungsentwurf zu erhalten, wurden in der Fachliteratur vernachlässigte Nichtidealitäten von FMCW-Radarsystemen modelliert. Dazu gehören Signalverzerrungen durch Kompression oder Intermodulation, der Einfluss der automatischen Verstärkungseinstellung sowie schmalbandige Störer und Nebenschwingungen. Die Ergebnisse der Modellierung wurden benutzt, um eine Spezifikation für den Schaltungsentwurf zu erhalten. Die Schätzung der Position aus gemessenen Abständen wurde über eine erweiterte Version des Gittersuchalgorithmus erreicht. Dieser nutzt die Abstandsmessdaten aus beiden Frequenzbändern. Der Algorithmus ist so entworfen, dass er effizient in einem eingebetteten System implementiert werden kann. Messungen zeigen eine maximale Reichweite des Systems von mindestens 245m. Die Genauigkeit von Abstandsmessungen im Freiland beträgt 8,2cm. Positionsmessungen wurden unter Verwendung beider Einzelbänder durchgeführt und mit den Ergebnissen des Zweiband-Gittersuchalgorithmus verglichen. Damit konnte eine starke Verbesserung der Positionsgenauigkeit erreicht werden. Die Genauigkeit in einem Innenraum mit einer Grundfläche von 276m² kann verbessert werden von 1,27m bei 2,4GHz und 1,86m bei 5,8GHz zu nur 0,38m im Zweibandverfahren. Das entspricht einer Verbesserung um einen Faktor von mindestens 3,3. In einem größeren Außenszenario mit einer Fläche von 4,8 km² verbessert sich die Genauigkeit um einen Faktor von mindestens 2,8 von 1,88m bei 2,4GHz und 5,93m bei 5,8GHz auf 0,68m bei Nutzung von Daten aus beiden Frequenzbändern

Radiation Tolerant Electronics, Volume II

Research on radiation tolerant electronics has increased rapidly over the last few years, resulting in many interesting approaches to model radiation effects and design radiation hardened integrated circuits and embedded systems. This research is strongly driven by the growing need for radiation hardened electronics for space applications, high-energy physics experiments such as those on the large hadron collider at CERN, and many terrestrial nuclear applications, including nuclear energy and safety management. With the progressive scaling of integrated circuit technologies and the growing complexity of electronic systems, their ionizing radiation susceptibility has raised many exciting challenges, which are expected to drive research in the coming decade.After the success of the first Special Issue on Radiation Tolerant Electronics, the current Special Issue features thirteen articles highlighting recent breakthroughs in radiation tolerant integrated circuit design, fault tolerance in FPGAs, radiation effects in semiconductor materials and advanced IC technologies and modelling of radiation effects

Digital Centric Multi-Gigabit SerDes Design and Verification

Advances in semiconductor manufacturing still lead to ever decreasing feature sizes and constantly allow higher degrees of integration in application specific integrated circuits (ASICs). Therefore the bandwidth requirements on the external interfaces of such systems on chips (SoC) are steadily growing. Yet, as the number of pins on these ASICs is not increasing in the same pace - known as pin limitation - the bandwidth per pin has to be increased. SerDes (Serializer/Deserializer) technology, which allows to transfer data serially at very high data rates of 25Gbps and more is a key technology to overcome pin limitation and exploit the computing power that can be achieved in todays SoCs. As such SerDes blocks together with the digital logic interfacing them form complex mixed signal systems, verification of performance and functional correctness is very challenging. In this thesis a novel mixed-signal design methodology is proposed, which tightly couples model and implementation in order to ensure consistency throughout the design cycles and hereby accelerate the overall implementation flow. A tool flow that has been developed is presented, which integrates well into state of the art electronic design automation (EDA) environments and enables the usage of this methodology in practice. Further, the design space of todays high-speed serial links is analyzed and an architecture is proposed, which pushes complexity into the digital domain in order to achieve robustness, portability between manufacturing processes and scaling with advanced node technologies. The all digital phase locked loop (PLL) and clock data recovery (CDR), which have been developed are described in detail. The developed design flow was used for the implementation of the SerDes architecture in a 28nm silicon process and proved to be indispensable for future projects

A superconducting bandpass delta-sigma modulator for direct analog-to-digital conversion of microwave radio

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.Includes bibliographical references (p. 291-305).This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Direct analog-to-digital conversion of multi-GHz radio frequency (RF) signals is the ultimate goal in software radio receiver design but remains a daunting challenge for any technology. This thesis examines the potential of superconducting technology for realizing RF analog-to-digital converters (ADCs) with improved performance. A bandpass delta-sigma (AE) modulator is an attractive architecture for digitizing narrowband signals with high linearity and a large signal-to-noise ratio (SNR). The design of a superconducting bandpass AE modulator presented here exploits several advantages of superconducting electronics: the high quality factor of resonators, the high sampling rates of comparators realized with Josephson junctions, natural quantization of voltage pulses, and high circuit sensitivity. Demonstration of a superconducting circuit operating at clock rates in the tens of GHz is often hindered by the difficulty of high speed interfacing with room-temperature test equipment. In this work, a test chip with integrated acquisition memory is used to simplify high speed testing in a cryogenic environment. The small size (256 bits) of the on-chip memory severely limits the frequency resolution of spectra based on standard fast Fourier transforms. Higher resolution spectra are obtained by "segmented correlation", a new method for testing ADCs. Two different techniques have been found for clocking the superconducting modulator at frequencies in the tens of GHz. In the first approach, an optical clocking technique was developed, in which picosecond laser pulses are delivered via optical fiber to an on-chip metal-semiconductor-metal (MSM) photodiode, whose output current pulses trigger the Josephson circuitry. In the second approach, the superconducting modulator is clocked by an on-chip Josephson oscillator.(cont.) These testing methods have been applied in the successful demonstration of a super-conducting bandpass AE modulator fabricated in a niobium integrated circuit process with 1 kA/cm2 critical current density for the Josephson junctions. At a 42.6 GHz sampling rate, the center frequency of the experimental modulator is 2.23 GHz, the measured SNR is 49 dB over a 20.8 MHz bandwidth, and a full-scale (FS) input is -17.4 dBm. At a 40.2 GHz sampling rate, the measured in-band noise is -57 dBFS over a 19.6 MHz bandwidth.by John Francis Bulzacchelli.Ph.D

Novel RF CMOS Integrated Circuits and Systems for Broadband Dielectric Spectroscopy

Broadband dielectric spectroscopy has proven to be a valuable technique for characterization of chemicals and biomaterials. It has the great potential to become an indispensable and cost-effective tool in point-of-care medical applications due to its label-free and non-invasive operation. However, most of the existing dielectric spectroscopy instruments require bulky, heavy and expensive measurement set-up, restricting their use to only special applications in industry and laboratories. Therefore, integrated dielectric spectroscopy on silicon capable of direct detection of chemicals/biomaterials' complex permittivity can yield significant cost and size reduction, system integration, portability, enormous processing, and high throughput. A CMOS wideband dielectric spectroscopy system is proposed for chemical and biological material characterization. The complex permittivity detection is performed using a configurable harmonic-rejecting receiver capable of indirectly measuring the complex admittance of sensing capacitor exposed to the material-under-test (MUT) and subject to RF signal excitation with a frequency range of 0.62-10 GHz. The sensing capacitor is embedded in a voltage divider topology with a fixed capacitor and the relative variations in the magnitude and phase of the voltages across the capacitors are used to find the real and imaginary parts of the permittivity. The sensor achieves an rms permittivity error of less than 1% over the entire operation bandwidth. Using a sub-harmonic mixing scheme, the system can perform complex permittivity measurements from 0.62 to 10 GHz while requiring an input signal source with frequency range of only from 5 to 10 GHz. Thereby, the permittivity measurement system can be easily made self-sustained by implementing a 5-10 GHz frequency synthesizer on the same chip. One of the key building blocks in such a frequency synthesizer is the voltage-controlled oscillator (VCO) which has to cover an octave of frequency range. A novel low-phase-noise wide-tuning range VCO is presented using a triple-band LC resonator. The implemented VCO in 0.18μm CMOS technology achieves a continuous tuning range of 86.7% from 5.12 GHz to 12.95 GHz while drawing 5 to 10 mA current from 1-V supply. The measured phase noise at 1 MHz offset from carrier frequencies of 5.9, 9.12 and 12.25 GHz is -122.9, -117.1 and -110.5 dBc/Hz, respectively. Also, a dual-band quadrature voltage-controlled oscillator (QVCO) is presented using a transformer-based high-order LC-ring resonator which inherently provides quadrature signals without requiring noisy coupling transistors as in traditional approaches. The proposed resonator shows two possible oscillation frequencies which are exploited to realize a wide-tuning range QVCO employing a mode-switching transistor network. Due to the use of transformers, the oscillator has minimal area penalty compared to the conventional designs. The implemented prototype in a 65-nm CMOS process achieves a continuous tuning range of 77.8% from 2.75 GHz to 6.25 GHz while consuming 9.7 to 15.6 mA current from 0.6-V supply. The measured phase noise figure-of-merit (FoM) at 1 MHz offset ranges from 184 dB to 188.2 dB throughout the entire tuning range. The QVCO also exhibits good quadrature accuracy with 1.5º maximum phase error and occupies a relatively small silicon area of 0.35 mm^2