A time-based energy-efficient analog-to-digital converter

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Includes bibliographical references (leaves 123-129).Dual-slope converters use time to perform analog-to-digital conversion but require 2N+1 clock cycles to achieve N bits of precision. We describe a novel algorithm that also uses time to perform analog-to-digital conversion but requires 5N clock cycles to achieve N bits of precision via a successive sub-ranging technique. The algorithm requires one asynchronous comparator, two capacitors, one current source, and a state machine. Amplification of two is achieved without the use of an explicit amplifier by simply doing things twice in time. The use of alternating Voltage-to-Time and Time-to-Voltage conversions provides natural error cancellation of comparator offset and delay, 1/f noise, and switching charge-injection. The use of few components and an effcient mechanism for amplification and error cancellation allow for energy-effcient operation: In a 0.35 [mu]m implementation, we were able to achieve 12 bits of DNL limited precision or 11 bits of thermal noise-limited precision at a sampling frequency of 31.25kHz with 75 [mu] W of total analog and digital power consumption. These numbers yield a thermal noise-limited energy-efficiency of 1.17pJ per quantization level making it one of the most energy-effcient converters to date in the 10 to 12 bit precision range.(cont.) This converter could be useful in low-power hearing aids after analog gain control has been performed on a microphone front-end. An 8 bit audio version of our converter in a 0.18 [mu] m process consumes 960nW and yields an energy-efficiency of 0.12pJ per quantization level, perhaps the lowest ever reported. This converter may be useful in biomedical and sensor-network applications where energy-efficiency is paramount. Our algorithm has inherent advantages in time-to-digital conversion. It can be generalized to easily digitize power-law functions of its input, and it can be used in an interleaved architecture if higher speed is desired.by Heemin Yi Yang.Ph.D

A study on wireless hearing aids system configuration and simulation

Master'sMASTER OF SCIENC

Energy autonomous systems : future trends in devices, technology, and systems

The rapid evolution of electronic devices since the beginning of the nanoelectronics era has brought about exceptional computational power in an ever shrinking system footprint. This has enabled among others the wealth of nomadic battery powered wireless systems (smart phones, mp3 players, GPS, …) that society currently enjoys. Emerging integration technologies enabling even smaller volumes and the associated increased functional density may bring about a new revolution in systems targeting wearable healthcare, wellness, lifestyle and industrial monitoring applications

Ultra low power wearable sleep diagnostic systems

Sleep disorders are studied using sleep study systems called Polysomnography that records several biophysical parameters during sleep. However, these are bulky and are typically located in a medical facility where patient monitoring is costly and quite inefficient. Home-based portable systems solve these problems to an extent but they record only a minimal number of channels due to limited battery life. To surmount this, wearable sleep system are desired which need to be unobtrusive and have long battery life. In this thesis, a novel sleep system architecture is presented that enables the design of an ultra low power sleep diagnostic system. This architecture is capable of extending the recording time to 120 hours in a wearable system which is an order of magnitude improvement over commercial wearable systems that record for about 12 hours. This architecture has in effect reduced the average power consumption of 5-6 mW per channel to less than 500 uW per channel. This has been achieved by eliminating sampled data architecture, reducing the wireless transmission rate and by moving the sleep scoring to the sensors. Further, ultra low power instrumentation amplifiers have been designed to operate in weak inversion region to support this architecture. A 40 dB chopper-stabilised low power instrumentation amplifiers to process EEG were designed and tested to operate from 1.0 V consuming just 3.1 uW for peak mode operation with DC servo loop. A 50 dB non-EEG amplifier continuous-time bandpass amplifier with a consumption of 400 nW was also fabricated and tested. Both the amplifiers achieved a high CMRR and impedance that are critical for wearable systems. Combining these amplifiers with the novel architecture enables the design of an ultra low power sleep recording system. This reduces the size of the battery required and hence enables a truly wearable system.Open Acces

Design and Implementation of Switching Voltage Integrated Circuits Based on Sliding Mode Control

The need for high performance circuits in systems with low-voltage and low-power requirements has exponentially increased during the few last years due to the sophistication and miniaturization of electronic components. Most of these circuits are required to have a very good efficiency behavior in order to extend the battery life of the device. This dissertation addresses two important topics concerning very high efficiency circuits with very high performance specifications. The first topic is the design and implementation of class D audio power amplifiers, keeping their inherent high efficiency characteristic while improving their linearity performance, reducing their quiescent power consumption, and minimizing the silicon area. The second topic is the design and implementation of switching voltage regulators and their controllers, to provide a low-cost, compact, high efficient and reliable power conversion for integrated circuits. The first part of this dissertation includes a short, although deep, analysis on class D amplifiers, their history, principles of operation, architectures, performance metrics, practical design considerations, and their present and future market distribution. Moreover, the harmonic distortion of open-loop class D amplifiers based on pulse-width modulation (PWM) is analyzed by applying the duty cycle variation technique for the most popular carrier waveforms giving an easy and practical analytic method to evaluate the class D amplifier distortion and determine its specifications for a given linearity requirement. Additionally, three class D amplifiers, with an architecture based on sliding mode control, are proposed, designed, fabricated and tested. The amplifiers make use of a hysteretic controller to avoid the need of complex overhead circuitry typically needed in other architectures to compensate non-idealities of practical implementations. The design of the amplifiers based on this technique is compact, small, reliable, and provides a performance comparable to the state-of-the-art class D amplifiers, but consumes only one tenth of quiescent power. This characteristic gives to the proposed amplifiers an advantage for applications with minimal power consumption and very high performance requirements. The second part of this dissertation presents the design, implementation, and testing of switching voltage regulators. It starts with a description and brief analysis on the power converters architectures. It outlines the advantages and drawbacks of the main topologies, discusses practical design considerations, and compares their current and future market distribution. Then, two different buck converters are proposed to overcome the most critical issue in switching voltage regulators: to provide a stable voltage supply for electronic devices, with good regulation voltage, high efficiency performance, and, most important, a minimum number of components. The first buck converter, which has been designed, fabricated and tested, is an integrated dual-output voltage regulator based on sliding mode control that provides a power efficiency comparable to the conventional solutions, but potentially saves silicon area and input filter components. The design is based on the idea of stacking traditional buck converters to provide multiple output voltages with the minimum number of switches. Finally, a fully integrated buck converter based on sliding mode control is proposed. The architecture integrates the external passive components to deliver a complete monolithic solution with minimal silicon area. The buck converter employs a poly-phase structure to minimize the output current ripple and a hysteretic controller to avoid the generation of an additional high frequency carrier waveform needed in conventional solutions. The simulated results are comparable to the state-of-the-art works even with no additional post-fabrication process to improve the converter performance

Efficient Low Power Headphone Driver

In recent years, the consumer electronics market for battery-powered devices such as smartphones and tablets has been rapidly expanding. The requirements for audio CODEC in these portable devices have extended from merely supporting voice calls to high-fidelity music playback. As a result, audio driver performance has become one of the most important differentiating factors among products from different suppliers. There are three basic performance metrics that are typically used to benchmark audio modules: the maximum delivered output power, the audio fidelity measured in terms of dynamic range, THD+N, and finally the battery life. Maximizing all three of these performance metrics has proven to be an exceptionally hard task as portrayed by the research publications.This work presents an attempt to push all three of these metrics together and provide an acceptable balance which is achieved by selecting the right topology. Conventionally, headphone drivers are designed using a linear amplifier topology for many reasons- most prominently- to achieve a superior THD+N and PSRR requirement which in the past was essentially the only key performance metric needed. This came at the expense of realizing mediocre power efficiency targets, thereby wasting battery life. This picture changed dramatically over the last decade with smartphones and other portable devices becoming the first choice of the young generation. These devices are extremely power hungry due to the unlimited functions and features they provide and therefore battery life has come to the spotlight as a key resource that need to be preserved. As a result, in this work a headphone driver is based on a switching topology that is able to deliver more than 230mW of power (or equivalently 2Vrms) to a 16Ω load while achieving better than -98dB of THD+N , more than 108dB of SNR, and about 108dB PSRR while still maintaining a peak power efficiency of more than 84%

Wireless power transfer for combined sensing and stimulation in implantable biomedical devices

Actuellement, il existe une forte demande de Headstage et de microsystèmes intégrés implantables pour étudier l’activité cérébrale de souris de laboratoire en mouvement libre. De tels dispositifs peuvent s’interfacer avec le système nerveux central dans les paradigmes électriques et optiques pour stimuler et surveiller les circuits neuronaux, ce qui est essentiel pour découvrir de nouveaux médicaments et thérapies contre des troubles neurologiques comme l’épilepsie, la dépression et la maladie de Parkinson. Puisque les systèmes implantables ne peuvent pas utiliser une batterie ayant une grande capacité en tant que source d’énergie primaire dans des expériences à long terme, la consommation d’énergie du dispositif implantable est l’un des principaux défis de ces conceptions. La première partie de cette recherche comprend notre proposition de la solution pour diminuer la consommation d’énergie des microcircuits implantables. Nous proposons un nouveau circuit de décalage de niveau qui convertit les niveaux de signaux sub-seuils en niveaux ultra-bas à haute vitesse en utilisant une très faible puissance et une petite zone de silicium, ce qui le rend idéal pour les applications de faible puissance. Le circuit proposé introduit une nouvelle topologie de décaleur de niveau de tension utilisant un condensateur de décalage de niveau pour augmenter la plage de tensions de conversion, tout en réduisant considérablement le retard de conversion. Le circuit proposé atteint un délai de propagation plus court et une zone de silicium plus petite pour une fréquence de fonctionnement et une consommation d’énergie donnée par rapport à d’autres solutions de circuit. Les résultats de mesure sont présentés pour le circuit proposé fabriqué dans un processus CMOS TSMC de 0,18- mm. Le circuit présenté peut convertir une large gamme de tensions d’entrée de 330 mV à 1,8 V et fonctionner sur une plage de fréquence de 100 Hz à 100 MHz. Il a un délai de propagation de 29 ns et une consommation d’énergie de 61,5 nW pour les signaux d’entrée de 0,4 V, à une fréquence de 500 kHz, surpassant les conceptions précédentes. La deuxième partie de cette recherche comprend nos systèmes de transfert d’énergie sans fil proposé pour les applications optogénétiques. L’optogénétique est la combinaison de la méthode génétique et optique d’excitation, d’enregistrement et de contrôle des neurones biologiques. Ce système combine plusieurs technologies telles que les MEMS et la microélectronique pour collecter et transmettre les signaux neuronaux et activer un stimulateur optique via une liaison sans fil. Puisque les stimulateurs optiques consomment plus de puissance que les stimulateurs électriques, l’interface utilise la transmission de puissance par induction en utilisant des moyens innovants au lieu de la batterie avec la petite capacité comme source d’énergie.Notre première contribution dans la deuxième partie fournit un système de cage domestique intelligent basé sur des barrettes multi-bobines superposées à travers un récepteur multicellulaire implantable mince de taille 1×1 cm2, implanté sous le cuir chevelu d’une souris de laboratoire, et unité de gestion de l’alimentation intégrée. Ce système inductif est conçu pour fournir jusqu’à 35,5 mW de puissance délivrée à un émetteur-récepteur full duplex de faible puissance entièrement intégré pour prendre en charge des implants neuronaux à haute densité et bidirectionnels. L’émetteur (TX) utilise une bande ultra-large à impulsions radio basée sur des approches de combinaison, et le récepteur (RX) utilise une topologie à bande étroite à incrémentation de 2,4 GHz. L’émetteur-récepteur proposé fournit un débit de données de liaison montante TX à 500 Mbits/s double et un débit de données de liaison descendante RX à 100 Mbits/s, et est entièrement intégré dans un processus CMOS TSMC de 0,18-mm d’une taille totale de 0,8 mm2 . La puissance peut être délivrée à partir d’un signal de porteuse de 13,56-MHz avec une efficacité globale de transfert de puissance supérieure à 5% sur une distance de séparation allant de 3 cm à 5 cm. Notre deuxième contribution dans les systèmes de collecte d’énergie porte sur la conception et la mise en oeuvre d’une cage domestique de transmission de puissance sans fil (WPT) pour une plate-forme de neurosciences entièrement sans fil afin de permettre des expériences optogénétiques ininterrompues avec des rongeurs de laboratoire vivants. La cage domestique WPT utilise un nouveau réseau hybride de transmetteurs de puissance (TX) et des résonateurs multi-bobines segmentés pour atteindre une efficacité de transmission de puissance élevée (PTE) et délivrer une puissance élevée sur des distances aussi élevées que 20 cm. Le récepteur de puissance à bobines multiples (RX) utilise une bobine RX d’un diamètre de 1 cm et une bobine de résonateur d’un diamètre de 1,5 cm. L’efficacité moyenne du transfert de puissance WPT est de 29, 4%, à une distance nominale de 7 cm, pour une fréquence porteuse de 13,56 MHz. Il a des PTE maximum et minimum de 50% et 12% le long de l’axe Z et peut délivrer une puissance constante de 74 mW pour alimenter le headstage neuronal miniature. En outre, un dispositif implantable intégré dans un processus CMOS TSMC de 0,18-mm a été conçu et introduit qui comprend 64 canaux d’enregistrement, 16 canaux de stimulation optique, capteur de température, émetteur-récepteur et unité de gestion de l’alimentation (PMU). Ce circuit est alimenté à l’intérieur de la cage du WPT à l’aide d’une bobine réceptrice d’un diamètre de 1,5 cm pour montrer les performances du circuit PMU. Deux tensions régulées de 1,8 V et 1 V fournissent 79 mW de puissance pour tout le système sur une puce. Notre dernière contribution est un système WPT insensible aux désalignements angulaires pour alimenter un headstage pour des applications optogénétiques qui a été précédemment proposé par le Laboratoire de Microsystèmes Biomédicaux (BioML-UL) à ULAVAL. Ce système est la version étendue de notre deuxième contribution aux systèmes de collecte d’énergie.Dans la version mise à jour, un récepteur de puissance multi-bobines utilise une bobine RX d’un diamètre de 1,0 cm et une nouvelle bobine de résonateur fendu d’un diamètre de 1,5 cm, qui résiste aux défauts d’alignement angulaires. Dans cette version qui utilise une cage d’animal plus petite que la dernière version, 4 résonateurs sont utilisés côté TX. De plus, grâce à la forme et à la position de la bobine de répéteur L3 du côté du récepteur, la liaison résonnante hybride présentée peut correctement alimenter la tête sans interruption causée par le désalignement angulaire dans toute la cage de la maison. Chaque 3 tours du répéteur RX a été enveloppé avec un diamètre de 1,5 cm, sous différents angles par rapport à la bobine réceptrice. Les résultats de mesure montrent un PTE maximum et minimum de 53 % et 15 %. La méthode proposée peut fournir une puissance constante de 82 mW pour alimenter le petit headstage neural pour les applications optogénétiques. De plus, dans cette version, la performance du système est démontrée dans une expérience in-vivo avec une souris ChR2 en mouvement libre qui est la première expérience optogénétique sans fil et sans batterie rapportée avec enregistrement électrophysiologique simultané et stimulation optogénétique. L’activité électrophysiologique a été enregistrée après une stimulation optogénétique dans le Cortex Cingulaire Antérieur (CAC) de la souris.Our first contribution in the second part provides a smart home-cage system based on overlapped multi-coil arrays through a thin implantable multi-coil receiver of 1×1 cm2 of size, implantable bellow the scalp of a laboratory mouse, and integrated power management circuits. This inductive system is designed to deliver up to 35.5 mW of power delivered to a fully-integrated, low-power full-duplex transceiver to support high-density and bidirectional neural implants. The transmitter (TX) uses impulse radio ultra-wideband based on an edge combining approach, and the receiver (RX) uses a 2.4- GHz on-off keying narrow band topology. The proposed transceiver provides dual-band 500-Mbps TX uplink data rate and 100-Mbps RX downlink data rate, and it is fully integrated into 0.18-mm TSMC CMOS process within a total size of 0.8 mm2. The power can be delivered from a 13.56-MHz carrier signal with an overall power transfer efficiency above 5% across a separation distance ranging from 3 cm to 5 cm. Our second contribution in power-harvesting systems deals with designing and implementation of a WPT home-cage for a fully wireless neuroscience platform for enabling uninterrupted optogenetic experiments with live laboratory rodents. The WPT home-cage uses a new hybrid parallel power transmitter (TX) coil array and segmented multi-coil resonators to achieve high power transmission efficiency (PTE) and deliver high power across distances as high as 20 cm. The multi-coil power receiver (RX) uses an RX coil with a diameter of 1 cm and a resonator coil with a diameter of 1.5 cm. The WPT home-cage average power transfer efficiency is 29.4%, at a nominal distance of 7 cm, for a power carrier frequency of 13.56-MHz. It has maximum and minimum PTE of 50% and 12% along the Z axis and can deliver a constant power of 74 mW to supply the miniature neural headstage. Also, an implantable device integrated into a 0.18-mm TSMC CMOS process has been designed and introduced which includes 64 recording channels, 16 optical stimulation channels, temperature sensor, transceiver, and power management unit (PMU). This circuit powered up inside the WPT home-cage using receiver coil with a diameter of 1.5 cm to show the performance of the PMU circuit. Two regulated voltages of 1.8 V and 1 V provide 79 mW of power for all the system on a chip. Our last contribution is an angular misalignment insensitive WPT system to power up a headstage which has been previously proposed by the Biomedical Microsystems Laboratory (BioML-UL) at ULAVAL for optogenetic applications. This system is the extended version of our second contribution in power-harvesting systems. In the updated version a multi-coil power receiver uses an RX coil with a diameter of 1.0 cm and a new split resonator coil with a diameter of 1.5 cm, which is robust against angular misalignment. In this version which is using a smaller animal home-cage than the last version, 4 resonators are used on the TX side. Also, thanks to the shape and position of the repeater coil of L3 on the receiver side, the presented hybrid resonant link can properly power up the headstage without interruption caused by the angular misalignment all over the home-cage. Each 3 turns of the RX repeater has been wrapped up with a diameter of 1.5 cm, in different angles compared to the receiver coil. Measurement results show a maximum and minimum PTE of 53 % and 15 %. The proposed method can deliver a constant power of 82 mW to supply the small neural headstage for the optogenetic applications. Additionally, in this version, the performance of the system is demonstrated within an in-vivo experiment with a freely moving ChR2 mouse which is the first fully wireless and batteryless optogenetic experiment reported with simultaneous electrophysiological recording and optogenetic stimulation. Electrophysiological activity was recorded after delivering optogenetic stimulation in the Anterior Cingulate Cortex (ACC) of the mouse.Currently, there is a high demand for Headstage and implantable integrated microsystems to study the brain activity of freely moving laboratory mice. Such devices can interface with the central nervous system in both electrical and optical paradigms for stimulating and monitoring neural circuits, which is critical to discover new drugs and therapies against neurological disorders like epilepsy, depression, and Parkinson’s disease. Since the implantable systems cannot use a battery with a large capacity as a primary source of energy in long-term experiments, the power consumption of the implantable device is one of the leading challenges of these designs. The first part of this research includes our proposed solution for decreasing the power consumption of the implantable microcircuits. We propose a novel level shifter circuit which converting subthreshold signal levels to super-threshold signal levels at high-speed using ultra low power and a small silicon area, making it well-suited for low-power applications such as wireless sensor networks and implantable medical devices. The proposed circuit introduces a new voltage level shifter topology employing a level-shifting capacitor to increase the range of conversion voltages, while significantly reducing the conversion delay. The proposed circuit achieves a shorter propagation delay and a smaller silicon area for a given operating frequency and power consumption compared to other circuit solutions. Measurement results are presented for the proposed circuit fabricated in a 0.18-mm TSMC CMOS process. The presented circuit can convert a wide range of the input voltages from 330 mV to 1.8 V, and operate over a frequency range of 100-Hz to 100-MHz. It has a propagation delay of 29 ns, and power consumption of 61.5 nW for input signals 0.4 V, at a frequency of 500-kHz, outperforming previous designs. The second part of this research includes our proposed wireless power transfer systems for optogenetic applications. Optogenetics is the combination of the genetic and optical method of excitation, recording, and control of the biological neurons. This system combines multiple technologies such as MEMS and microelectronics to collect and transmit the neuronal signals and to activate an optical stimulator through a wireless link. Since optical stimulators consume more power than electrical stimulators, the interface employs induction power transmission using innovative means instead of the battery with the small capacity as a power source

Low Power Decoding Circuits for Ultra Portable Devices

A wide spread of existing and emerging battery driven wireless devices do not necessarily demand high data rates. Rather, ultra low power, portability and low cost are the most desired characteristics. Examples of such applications are wireless sensor networks (WSN), body area networks (BAN), and a variety of medical implants and health-care aids. Being small, cheap and low power for the individual transceiver nodes, let those to be used in abundance in remote places, where access for maintenance or recharging the battery is limited. In such scenarios, the lifetime of the battery, in most cases, determines the lifetime of the individual nodes. Therefore, energy consumption has to be so low that the nodes remain operational for an extended period of time, even up to a few years. It is known that using error correcting codes (ECC) in a wireless link can potentially help to reduce the transmit power considerably. However, the power consumption of the coding-decoding hardware itself is critical in an ultra low power transceiver node. Power and silicon area overhead of coding-decoding circuitry needs to be kept at a minimum in the total energy and cost budget of the transceiver node. In this thesis, low power approaches in decoding circuits in the framework of the mentioned applications and use cases are investigated. The presented work is based on the 65nm CMOS technology and is structured in four parts as follows: In the first part, goals and objectives, background theory and fundamentals of the presented work is introduced. Also, the ECC block in coordination with its surrounding environment, a low power receiver chain, is presented. Designing and implementing an ultra low power and low cost wireless transceiver node introduces challenges that requires special considerations at various levels of abstraction. Similarly, a competitive solution often occurs after a conclusive design space exploration. The proposed decoder circuits in the following parts are designed to be embedded in the low power receiver chain, that is introduced in the first part. Second part, explores analog decoding method and its capabilities to be embedded in a compact and low power transceiver node. Analog decod- ing method has been theoretically introduced over a decade ago that followed with early proof of concept circuits that promised it to be a feasible low power solution. Still, with the increased popularity of low power sensor networks, it has not been clear how an analog decoding approach performs in terms of power, silicon area, data rate and integrity of calculations in recent technologies and for low data rates. Ultra low power budget, small size requirement and more relaxed demands on data rates suggests a decoding circuit with limited complexity. Therefore, the four-state (7,5) codes are considered for hardware implementation. Simulations to chose the critical design factors are presented. Consequently, to evaluate critical specifications of the decoding circuit, three versions of analog decoding circuit with different transistor dimensions fabricated. The measurements results reveal different trade-off possibilities as well as the potentials and limitations of the analog decoding approach for the target applications. Measurements seem to be crucial, since the available computer-aided design (CAD) tools provide limited assistance and precision, given the amount of calculations and parameters that has to be included in the simulations. The largest analog decoding core (AD1) takes 0.104mm2 on silicon and the other two (AD2 and AD3) take 0.035mm2 and 0.015mm2, respectively. Consequently, coding gain in trade-off with silicon area and throughput is presented. The analog decoders operate with 0.8V supply. The achieved coding gain is 2.3 dB at bit error rates (BER)=0.001 and 10 pico-Joules per bit (pJ/b) energy efficiency is reached at 2 Mbps. Third part of this thesis, proposes an alternative low power digital decoding approach for the same codes. The desired compact and low power goal has been pursued by designing an equivalent digital decoding circuit that is fabricated in 65nm CMOS technology and operates in low voltage (near-threshold) region. The architecture of the design is optimized in system and circuit levels to propose a competitive digital alternative. Similarly, critical specifications of the decoder in terms of power, area, data rate (speed) and integrity are reported according to the measurements. The digital implementation with 0.11mm2 area, consumes minimum energy at 0.32V supply which gives 9 pJ/b energy efficiency at 125 kb/s and 2.9 dB coding gain at BER=0.001. The forth and last part, compares the proposed design alternatives based on the fabricated chips and the results attained from the measurements to conclude the most suitable solution for the considered target applications. Advantages and disadvantages of both approaches are discussed. Possible extensions of this work is introduced as future work

VLSI Circuits for Bidirectional Neural Interfaces

Medical devices that deliver electrical stimulation to neural tissue are important clinical tools that can augment or replace pharmacological therapies. The success of such devices has led to an explosion of interest in the field, termed neuromodulation, with a diverse set of disorders being targeted for device-based treatment. Nevertheless, a large degree of uncertainty surrounds how and why these devices are effective. This uncertainty limits the ability to optimize therapy and gives rise to deleterious side effects. An emerging approach to improve neuromodulation efficacy and to better understand its mechanisms is to record bioelectric activity during stimulation. Understanding how stimulation affects electrophysiology can provide insights into disease, and also provides a feedback signal to autonomously tune stimulation parameters to improve efficacy or decrease side-effects. The aims of this work were taken up to advance the state-of-the-art in neuro-interface technology to enable closed-loop neuromodulation therapies. Long term monitoring of neuronal activity in awake and behaving subjects can provide critical insights into brain dynamics that can inform system-level design of closed-loop neuromodulation systems. Thus, first we designed a system that wirelessly telemetered electrocorticography signals from awake-behaving rats. We hypothesized that such a system could be useful for detecting sporadic but clinically relevant electrophysiological events. In an 18-hour, overnight recording, seizure activity was detected in a pre-clinical rodent model of global ischemic brain injury. We subsequently turned to the design of neurostimulation circuits. Three critical features of neurostimulation devices are safety, programmability, and specificity. We conceived and implemented a neurostimulator architecture that utilizes a compact on-chip circuit for charge balancing (safety), digital-to-analog converter calibration (programmability) and current steering (specificity). Charge balancing accuracy was measured at better than 0.3%, the digital-to-analog converters achieved 8-bit resolution, and physiological effects of current steering stimulation were demonstrated in an anesthetized rat. Lastly, to implement a bidirectional neural interface, both the recording and stimulation circuits were fabricated on a single chip. In doing so, we implemented a low noise, ultra-low power recording front end with a high dynamic range. The recording circuits achieved a signal-to-noise ratio of 58 dB and a spurious-free dynamic range of better than 70 dB, while consuming 5.5 μW per channel. We demonstrated bidirectional operation of the chip by recording cardiac modulation induced through vagus nerve stimulation, and demonstrated closed-loop control of cardiac rhythm