Cycle-accurate evaluation of reconfigurable photonic networks-on-chip

There is little doubt that the most important limiting factors of the performance of next-generation Chip Multiprocessors (CMPs) will be the power efficiency and the available communication speed between cores. Photonic Networks-on-Chip (NoCs) have been suggested as a viable route to relieve the off- and on-chip interconnection bottleneck. Low-loss integrated optical waveguides can transport very high-speed data signals over longer distances as compared to on-chip electrical signaling. In addition, with the development of silicon microrings, photonic switches can be integrated to route signals in a data-transparent way. Although several photonic NoC proposals exist, their use is often limited to the communication of large data messages due to a relatively long set-up time of the photonic channels. In this work, we evaluate a reconfigurable photonic NoC in which the topology is adapted automatically (on a microsecond scale) to the evolving traffic situation by use of silicon microrings. To evaluate this system's performance, the proposed architecture has been implemented in a detailed full-system cycle-accurate simulator which is capable of generating realistic workloads and traffic patterns. In addition, a model was developed to estimate the power consumption of the full interconnection network which was compared with other photonic and electrical NoC solutions. We find that our proposed network architecture significantly lowers the average memory access latency (35% reduction) while only generating a modest increase in power consumption (20%), compared to a conventional concentrated mesh electrical signaling approach. When comparing our solution to high-speed circuit-switched photonic NoCs, long photonic channel set-up times can be tolerated which makes our approach directly applicable to current shared-memory CMPs

Simulation of ultrasonic lamb wave generation, propagation and detection for an air coupled robotic scanner

A computer simulator, to facilitate the design and assessment of a reconfigurable, air-coupled ultrasonic scanner is described and evaluated. The specific scanning system comprises a team of remote sensing agents, in the form of miniature robotic platforms that can reposition non-contact Lamb wave transducers over a plate type of structure, for the purpose of non-destructive evaluation (NDE). The overall objective is to implement reconfigurable array scanning, where transmission and reception are facilitated by different sensing agents which can be organised in a variety of pulse-echo and pitch-catch configurations, with guided waves used to generate data in the form of 2-D and 3-D images. The ability to reconfigure the scanner adaptively requires an understanding of the ultrasonic wave generation, its propagation and interaction with potential defects and boundaries. Transducer behaviour has been simulated using a linear systems approximation, with wave propagation in the structure modelled using the local interaction simulation approach (LISA). Integration of the linear systems and LISA approaches are validated for use in Lamb wave scanning by comparison with both analytic techniques and more computationally intensive commercial finite element/difference codes. Starting with fundamental dispersion data, the paper goes on to describe the simulation of wave propagation and the subsequent interaction with artificial defects and plate boundaries, before presenting a theoretical image obtained from a team of sensing agents based on the current generation of sensors and instrumentation

Full-Duplex Systems Using Multi-Reconfigurable Antennas

Full-duplex systems are expected to achieve 100% rate improvement over half-duplex systems if the self-interference signal can be significantly mitigated. In this paper, we propose the first full-duplex system utilizing Multi-Reconfigurable Antenna (MRA) with ?90% rate improvement compared to half-duplex systems. MRA is a dynamically reconfigurable antenna structure, that is capable of changing its properties according to certain input configurations. A comprehensive experimental analysis is conducted to characterize the system performance in typical indoor environments. The experiments are performed using a fabricated MRA that has 4096 configurable radiation patterns. The achieved MRA-based passive self-interference suppression is investigated, with detailed analysis for the MRA training overhead. In addition, a heuristic-based approach is proposed to reduce the MRA training overhead. The results show that at 1% training overhead, a total of 95dB self-interference cancellation is achieved in typical indoor environments. The 95dB self-interference cancellation is experimentally shown to be sufficient for 90% full-duplex rate improvement compared to half-duplex systems.Comment: Submitted to IEEE Transactions on Wireless Communication

A spectrally-accurate FVTD technique for complicated amplification and reconfigurable filtering EMC devices

The consistent and computationally economical analysis of demanding amplification and filtering structures is introduced in this paper via a new spectrally-precise finite-volume time-domain algorithm. Combining a family of spatial derivative approximators with controllable accuracy in general curvilinear coordinates, the proposed method employs a fully conservative field flux formulation to derive electromagnetic quantities in areas with fine structural details. Moreover, the resulting 3-D operators assign the appropriate weight to each spatial stencil at arbitrary media interfaces, while for periodic components the domain is systematically divided to a number of nonoverlapping subdomains. Numerical results from various real-world configurations verify our technique and reveal its universality

Coarse-grained reconfigurable array architectures

Coarse-Grained Reconfigurable Array (CGRA) architectures accelerate the same inner loops that benefit from the high ILP support in VLIW architectures. By executing non-loop code on other cores, however, CGRAs can focus on such loops to execute them more efficiently. This chapter discusses the basic principles of CGRAs, and the wide range of design options available to a CGRA designer, covering a large number of existing CGRA designs. The impact of different options on flexibility, performance, and power-efficiency is discussed, as well as the need for compiler support. The ADRES CGRA design template is studied in more detail as a use case to illustrate the need for design space exploration, for compiler support and for the manual fine-tuning of source code

Achieving High Speed CFD simulations: Optimization, Parallelization, and FPGA Acceleration for the unstructured DLR TAU Code

Today, large scale parallel simulations are fundamental tools to handle complex problems. The number of processors in current computation platforms has been recently increased and therefore it is necessary to optimize the application performance and to enhance the scalability of massively-parallel systems. In addition, new heterogeneous architectures, combining conventional processors with specific hardware, like FPGAs, to accelerate the most time consuming functions are considered as a strong alternative to boost the performance. In this paper, the performance of the DLR TAU code is analyzed and optimized. The improvement of the code efficiency is addressed through three key activities: Optimization, parallelization and hardware acceleration. At first, a profiling analysis of the most time-consuming processes of the Reynolds Averaged Navier Stokes flow solver on a three-dimensional unstructured mesh is performed. Then, a study of the code scalability with new partitioning algorithms are tested to show the most suitable partitioning algorithms for the selected applications. Finally, a feasibility study on the application of FPGAs and GPUs for the hardware acceleration of CFD simulations is presented

From MARTE to Reconfigurable NoCs: A model driven design methodology

Due to the continuous exponential rise in SoC's design complexity, there is a critical need to find new seamless methodologies and tools to handle the SoC co-design aspects. We address this issue and propose a novel SoC co-design methodology based on Model Driven Engineering and the MARTE (Modeling and Analysis of Real-Time and Embedded Systems) standard proposed by Object Management Group, to raise the design abstraction levels. Extensions of this standard have enabled us to move from high level specifications to execution platforms such as reconfigurable FPGAs. In this paper, we present a high level modeling approach that targets modern Network on Chips systems. The overall objective: to perform system modeling at a high abstraction level expressed in Unified Modeling Language (UML); and afterwards, transform these high level models into detailed enriched lower level models in order to automatically generate the necessary code for final FPGA synthesis

Trade-off between power and bandwidth consumption in a reconfigurable xhaul network architecture

The increasing number of wireless devices, the high required traffic bandwidth, and power consumption will lead to a revolution of mobile access networks, which is not a simple evolution of traditional ones. Cloud radio access network technologies are seen as promising solution in order to deal with the heavy requirements defined for 5G mobile networks. The introduction of the common public radio interface (CPRI) technology allows for a centralization in BaseBand unit (BBU) of some access functions with advantages in terms of power consumption saving when switching off algorithms are implemented. Unfortunately, the advantages of the CPRI technology are to be paid with an increase in required bandwidth to carry the traffic between the BBU and the radio remote unit (RRU), in which only the radio functions are implemented. For this reason, a tradeoff solution between power and bandwidth consumption is proposed and evaluated. The proposed solution consists of: 1) handling the traffic generated by the users through both RRU and traditional radio base stations (RBS) and 2) carrying the traffic generated by the RRU and RBS (CPRI and Ethernet flows) with a reconfigurable network. The proposed solution is investigated under the lognormal spatial traffic distribution assumption. After proposing resource dimensioning analytical models validated by simulation, we show how the sum of the bandwidth and power consumption may be minimized with the deployment of a given percentage of RRU. For instance we show how in 5G traffic scenarios this percentage can vary from 30% to 50% according to total traffic amount handled by a switching node of the reconfigurable network