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    A Scan-BIST Structure to Test Delay Faults in Sequential Circuits

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    International audienceDelay testing that requires the application of consecutive two-pattern tests is not an easy task in a scan-based environment. This paper proposes a novel approach to the delay fault testing problem in scan-based sequential circuits. This solution is based on the combination of a BIST structure with a scan-based design to apply delay test pairs to the circuit under test
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