Performance Modeling of Parallel Applications on MPSoCs

In this paper we present a new technique for automatically measuring the performance of tasks, functions or arbitrary parts of a program on a multiprocessor embedded system. The technique instruments the tasks described by OpenMP, used to represent the task parallelism, while ad hoc pragmas in the source indicate other pieces of code to profile. The annotations and the instrumentation are completely target-independent, so the same code can be measured on different target architectures, on simulators or on prototypes. We validate the approach on a single and on a dual LEON 3 platform synthesized on FPGA, demonstrating a low instrumentation overhead. We show how the information obtained with this technique can be easily exploited in a hardware/software design space exploration tool, by estimating, with good accuracy, the speed-up of a parallel application given the profiling on the single processor prototype

EPC Enacted: Integration in an Industrial Toolbox and Use against a Railway Application

Measurement-based timing analysis approaches are increasingly making their way into several industrial domains on account of their good cost-benefit ratio. The trustworthiness of those methods, however, suffers from the limitation that their results are only valid for the particular paths and execution conditions that the user is able to explore with the available input vectors. It is generally not possible to guarantee that the collected measurements are fully representative of the worst-case timing behaviour. In the context of measurement-based probabilistic timing analysis, the Extended Path Coverage (EPC) approach has been recently proposed as a means to extend the representativeness of measurement observations, to obtain the same effect of full path coverage. At the time of its first publication, EPC had not reached an implementation maturity that could be trialled industrially. In this work we analyze the practical implications of using EPC with real-world applications, and discuss the challenges in integrating it in an industrial-quality toolchain. We show that we were able to meet EPC requirements and successfully evaluate the technique on a real Railway application, on top of a commercial toolchain and full execution stack.This work has received funding from the European Community’s Seventh Framework Programme [FP7/2007-2013] under grant agreement 611085 (PROXIMA, www.proxima-project.eu). This work has also been partially supported by the Spanish Ministry of Economy and Competitiveness (MINECO) under grant TIN2015-65316-P and the HiPEAC Network of Excellence. Jaume Abella has been partially supported by the MINECO under Ramon y Cajal postdoctoral fellowship number RYC-2013-14717. The authors are grateful to Antoine Colin from Rapita Ltd. for his precious support.Peer ReviewedPostprint (author's final draft

Performance modeling of embedded applications with zero architectural knowledge

Performance estimation is a key step in the development of an embedded system. Normally, the performance evaluation is performed using a simulator or a performance mathematical model of the target architecture. However, both these approaches are usually based on the knowledge of the architectural details of the target. In this paper we present a methodology for automatically building an analytical model to estimate the performance of an application on a generic processor without requiring any information about the processor architecture but the one provided by the GNU GCC Intermediate Representation. The proposed methodology exploits the linear regression technique based on an application analysis performed on the Register Transfer Level internal representation of the GNU GCC compiler. The benefits of working with this type of model and with this intermediate representation are three: we take into account most of the compiler optimizations, we implicitly consider some architectural characteristics of the target processor and we can easily estimate the performance of portions of the specification. We validate our approach by evaluating with cross-validation technique the accuracy and the generality of the performance models built for the ARM926EJ-S and the LEON3 processor

Instrumenting and analyzing platform-independent communication in applications

The performance of microprocessors is limited by communication. This limitation, sometimes alluded to as the memory wall, refers to the hardware-level cost of communicating with memory. Recent studies have found that the promise of speedup from transistor scaling, or employing heterogeneous processors, such as GPUs, is diminished when such hardware communication costs are included. Based on the insight that hardware communication at run-time is a manifestation of communication in software, this dissertation proposes that automatically capturing and classifying software-level communication is the first step in performing fast, early-stage design space exploration of future multicore systems. Software-level communication refers to the exchange of data between software entities such as functions, threads or basic blocks. Communication classification helps differentiate the first-time use from the reuse of communicated data, and distinguishes between communication external to a software entity and local communication within a software entity. We present Sigil, a novel tool that automatically captures and classifies software-level communication in an efficient way. Due to its platform-independent nature, software-level communication can be useful during the early-stage design of future multicore systems. Using the two different representations of output data that Sigil produces, we show that the measurement of software-level communication can be used to analyze i) function-level interaction in single-threaded programs to determine which specialized logic can be included in future heterogeneous multicore systems, and ii) thread-level interaction in multi-threaded programs to aid in chip multi-processor(CMP) design space exploration.Ph.D., Electrical Engineering -- Drexel University, 201

High-Level Synthesis Hardware Design for FPGA-Based Accelerators: Models, Methodologies, and Frameworks

Hardware accelerators based on field programmable gate array (FPGA) and system on chip (SoC) devices have gained attention in recent years. One of the main reasons is that these devices contain reconfigurable logic, which makes them feasible for boosting the performance of applications. High-level synthesis (HLS) tools facilitate the creation of FPGA code from a high level of abstraction using different directives to obtain an optimized hardware design based on performance metrics. However, the complexity of the design space depends on different factors such as the number of directives used in the source code, the available resources in the device, and the clock frequency. Design space exploration (DSE) techniques comprise the evaluation of multiple implementations with different combinations of directives to obtain a design with a good compromise between different metrics. This paper presents a survey of models, methodologies, and frameworks proposed for metric estimation, FPGA-based DSE, and power consumption estimation on FPGA/SoC. The main features, limitations, and trade-offs of these approaches are described. We also present the integration of existing models and frameworks in diverse research areas and identify the different challenges to be addressed

Abordagem de Anotações para o Suporte da Gestão Energética de Software em Modelos AMALTHEA

The automotive industry is continuously introducing innovative software features to provide more efficient, safe, and comfortable solutions. Despite the several benefits to the consumer, the evolution of automotive software is also reflected in several challenges, presenting a growing complexity that hinders its development and integration. The adoption of standards and appropriate development methods becomes essential to meet the requirements of the industry. Furthermore, the expansion of automotive software systems is also driving a considerable growth in the number of electronic components installed in a vehicle, which has a significant impact on the electric energy consumption. Thus, the focus on non-functional energy requirements has become increasingly important. This work presents a study focused on the evolution of automotive software considering the development standards, methodologies, as well as approaches for energy requirements management. We propose an automatic and self-contained approach for the support of energy properties management, adopting the model-based open-source framework AMALTHEA. From the analysis of execution or simulation traces, the energy consumption estimation is provided at a fine-grained level and annotated in AMALTHEA models. Thus, we enable the energy analysis and management of the system throughout the entire lifecycle. Additionally, this solution is in line with the AUTOSAR Adaptive standard, allowing the development of energy management strategies for automatic, dynamic, and adaptive systems.A indústria automotiva encontra-se constantemente a introduzir funcionalidades inovadoras através de software, para oferecer soluções mais eficientes, seguras e confortáveis. Apesar dos diversos benefícios para o consumidor, a evolução do software automóvel também se reflete em diversos desafios, apresentando uma crescente complexidade que dificulta o seu desenvolvimento e integração. Desta forma, a adoção de normas e metodologias adequadas para o seu desenvolvimento torna-se essencial para cumprir os requisitos do setor. Adicionalmente, esta expansão das funcionalidades suportadas por software é fonte de um aumento considerável do número de componentes eletrónicos instalados em automóveis. Consequentemente, existe um impacto significativo no consumo de energia elétrica dos sistemas automóveis, sendo cada vez mais relevante o foco nos requisitos não-funcionais deste domínio. Este trabalho apresenta um estudo focado na evolução do software automotivo tendo em conta os padrões e metodologias de desenvolvimento desta área, bem como abordagens para a gestão de requisitos de energia. Através da adoção da ferramenta AMALTHEA, uma plataforma open-source de desenvolvimento baseado em modelos, é proposta uma abordagem automática e independente para a análise de propriedades energéticas. A partir da análise de traços de execução ou de simulação, é produzida uma estimativa pormenorizada do consumo de energia, sendo esta anotada em modelos AMALTHEA. Desta forma, torna-se possível a análise e gestão energética ao longo de todo o ciclo de vida do sistema. Salienta-se que a solução se encontra alinhada com a norma AUTOSAR Adaptive, permitindo o desenvolvimento de estratégias para a gestão energética de sistemas automáticos, dinâmicos e adaptativos

Chapter SW Annotation Techniques and RTOS Modelling for Native Simulation of Heterogeneous Embedded Systems

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