A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS

© 2017 Elsevier Ltd. All rights reserved.A 0.1–5.0 GHz flexible software-defined radio (SDR) receiver with digitally assisted calibration is presented, employing a zero-IF/low-IF reconfigurable architecture for both wideband and narrowband applications. The receiver composes of a main-path based on a current-mode mixer for low noise, a high linearity sub-path based on a voltage-mode passive mixer for out-of-band rejection, and a harmonic rejection (HR) path with vector gain calibration. A dual feedback LNA with “8” shape nested inductor structure, a cascode inverter-based TCA with miller feedback compensation, and a class-AB full differential Op-Amp with Miller feed-forward compensation and QFG technique are proposed. Digitally assisted calibration methods for HR, IIP2 and image rejection (IR) are presented to maintain high performance over PVT variations. The presented receiver is implemented in 65 nm CMOS with 5.4 mm2 core area, consuming 9.6–47.4 mA current under 1.2 V supply. The receiver main path is measured with +5 dB m/+5dBm IB-IIP3/OB-IIP3 and +61dBm IIP2. The sub-path achieves +10 dB m/+18dBm IB-IIP3/OB-IIP3 and +62dBm IIP2, as well as 10 dB RF filtering rejection at 10 MHz offset. The HR-path reaches +13 dB m/+14dBm IB-IIP3/OB-IIP3 and 62/66 dB 3rd/5th-order harmonic rejection with 30–40 dB improvement by the calibration. The measured sensitivity satisfies the requirements of DVB-H, LTE, 802.11 g, and ZigBee.Peer reviewedFinal Accepted Versio

Reconfigurable Receiver Front-Ends for Advanced Telecommunication Technologies

The exponential growth of converging technologies, including augmented reality, autonomous vehicles, machine-to-machine and machine-to-human interactions, biomedical and environmental sensory systems, and artificial intelligence, is driving the need for robust infrastructural systems capable of handling vast data volumes between end users and service providers. This demand has prompted a significant evolution in wireless communication, with 5G and subsequent generations requiring exponentially improved spectral and energy efficiency compared to their predecessors. Achieving this entails intricate strategies such as advanced digital modulations, broader channel bandwidths, complex spectrum sharing, and carrier aggregation scenarios. A particularly challenging aspect arises in the form of non-contiguous aggregation of up to six carrier components across the frequency range 1 (FR1). This necessitates receiver front-ends to effectively reject out-of-band (OOB) interferences while maintaining high-performance in-band (IB) operation. Reconfigurability becomes pivotal in such dynamic environments, where frequency resource allocation, signal strength, and interference levels continuously change. Software-defined radios (SDRs) and cognitive radios (CRs) emerge as solutions, with direct RF-sampling receivers offering a suitable architecture in which the frequency translation is entirely performed in digital domain to avoid analog mixing issues. Moreover, direct RF- sampling receivers facilitate spectrum observation, which is crucial to identify free zones, and detect interferences. Acoustic and distributed filters offer impressive dynamic range and sharp roll off characteristics, but their bulkiness and lack of electronic adjustment capabilities limit their practicality. Active filters, on the other hand, present opportunities for integration in advanced CMOS technology, addressing size constraints and providing versatile programmability. However, concerns about power consumption, noise generation, and linearity in active filters require careful consideration.This thesis primarily focuses on the design and implementation of a low-voltage, low-power RFFE tailored for direct sampling receivers in 5G FR1 applications. The RFFE consists of a balun low-noise amplifier (LNA), a Q-enhanced filter, and a programmable gain amplifier (PGA). The balun-LNA employs noise cancellation, current reuse, and gm boosting for wideband gain and input impedance matching. Leveraging FD-SOI technology allows for programmable gain and linearity via body biasing. The LNA's operational state ranges between high-performance and high-tolerance modes, which are apt for sensitivityand blocking tests, respectively. The Q-enhanced filter adopts noise-cancelling, current-reuse, and programmable Gm-cells to realize a fourth-order response using two resonators. The fourth-order filter response is achieved by subtracting the individual response of these resonators. Compared to cascaded and magnetically coupled fourth-order filters, this technique maintains the large dynamic range of second-order resonators. Fabricated in 22-nm FD-SOI technology, the RFFE achieves 1%-40% fractional bandwidth (FBW) adjustability from 1.7 GHz to 6.4 GHz, 4.6 dB noise figure (NF) and an OOB third-order intermodulation intercept point (IIP3) of 22 dBm. Furthermore, concerning the implementation uncertainties and potential variations of temperature and supply voltage, design margins have been considered and a hybrid calibration scheme is introduced. A combination of on-chip and off-chip calibration based on noise response is employed to effectively adjust the quality factors, Gm-cells, and resonance frequencies, ensuring desired bandpass response. To optimize and accelerate the calibration process, a reinforcement learning (RL) agent is used.Anticipating future trends, the concept of the Q-enhanced filter extends to a multiple-mode filter for 6G upper mid-band applications. Covering the frequency range from 8 to 20 GHz, this RFFE can be configured as a fourth-order dual-band filter, two bandpass filters (BPFs) with an OOB notch, or a BPF with an IB notch. In cognitive radios, the filter’s transmission zeros can be positioned with respect to the carrier frequencies of interfering signals to yield over 50 dB blocker rejection

Energy-Efficient Wireless Circuits and Systems for Internet of Things

As the demand of ultra-low power (ULP) systems for internet of thing (IoT) applications has been increasing, large efforts on evolving a new computing class is actively ongoing. The evolution of the new computing class, however, faced challenges due to hard constraints on the RF systems. Significant efforts on reducing power of power-hungry wireless radios have been done. The ULP radios, however, are mostly not standard compliant which poses a challenge to wide spread adoption. Being compliant with the WiFi network protocol can maximize an ULP radio’s potential of utilization, however, this standard demands excessive power consumption of over 10mW, that is hardly compatible with in ULP systems even with heavy duty-cycling. Also, lots of efforts to minimize off-chip components in ULP IoT device have been done, however, still not enough for practical usage without a clean external reference, therefore, this limits scaling on cost and form-factor of the new computer class of IoT applications. This research is motivated by those challenges on the RF systems, and each work focuses on radio designs for IoT applications in various aspects. First, the research covers several endeavors for relieving energy constraints on RF systems by utilizing existing network protocols that eventually meets both low-active power, and widespread adoption. This includes novel approaches on 802.11 communication with articulate iterations on low-power RF systems. The research presents three prototypes as power-efficient WiFi wake-up receivers, which bridges the gap between industry standard radios and ULP IoT radios. The proposed WiFi wake-up receivers operate with low power consumption and remain compatible with the WiFi protocol by using back-channel communication. Back-channel communication embeds a signal into a WiFi compliant transmission changing the firmware in the access point, or more specifically just the data in the payload of the WiFi packet. With a specific sequence of data in the packet, the transmitter can output a signal that mimics a modulation that is more conducive for ULP receivers, such as OOK and FSK. In this work, low power mixer-first receivers, and the first fully integrated ultra-low voltage receiver are presented, that are compatible with WiFi through back-channel communication. Another main contribution of this work is in relieving the integration challenge of IoT devices by removing the need for external, or off-chip crystals and antennas. This enables a small form-factor on the order of mm3-scale, useful for medical research and ubiquitous sensing applications. A crystal-less small form factor fully integrated 60GHz transceiver with on-chip 12-channel frequency reference, and good peak gain dual-mode on-chip antenna is presented.PHDElectrical and Computer EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/162975/1/jaeim_1.pd

대역 외 방해신호에 내성을 가지는 광대역 수신기에 관한 연구

학위논문 (박사)-- 서울대학교 대학원 : 공과대학 전기·컴퓨터공학부, 2018. 2. 남상욱.In this thesis, a study of wideband receivers as one of the practical SDR receiver implementations is presented. The out-of-band interference signal (or blocker), which is the biggest problem of the wideband receiver is investigated, and have studied how to effectively remove it. As a result of reviewing previous studies, we have developed a wideband receiver based on the current-mode receiver structure and attempted to eliminate the blocker. The contents of the step-by-step research are as follows. First, attention was paid to the linearity of a low-noise transconductance amplifier (LNTA), which is the base block of current-mode receivers. In current-mode receivers, the LNTA should have a high transconductance (Gm) value to achieve a low noise figure, but a high Gm value results in low linearity. To solve this trade-off, we proposed a linearization method of transconductors. The proposed technique eliminates the third-order intermodulation distortion (IMD3) in a feed-forward manner using two paths. A transconductor having a transconductance of 2Gm is disposed in the main path, and an amplifier having a gain of ∛2 and a Gm-sized transconductor are located in the auxiliary path. This structure allows for some fundamental signal loss but cancel the IMD3 component at the output. As a result, the entire transconductor circuit can have high linearity due to the removed IMD3 component. We have designed a reconfigurable high-pass filter using a linearized transconductor and have demonstrated its performance. The fabricated circuit achieved a high input-referred third-order intercept point(IIP3) performance of 19.4 dBm. Then, a further improved linearized transconductor is designed. Since the linearized transconductors have a high noise figure due to the additional circuitry used for linearization, we have proposed a more suitable form for application to LNTA through noise figure analysis. The improved LNTA is designed to operate in low noise mode when there is no blocker, and can be switched to operate in high linearity mode when the blocker exists. We also applied noise cancelling techniques to the receiver to improve the noise figure performance of the wideband receiver circuit. A feedback path has been added to the current-mode receiver structure consisting of the LNTA, the mixer and the baseband transimpedance amplifier (TIA), and the noise signal can be detected using this path. This feedback path also maintains the input matching of the receiver to 50 Ω in a wide bandwidth. By adding an auxiliary path to the receiver, the in-band signal is amplified and the detected noise is removed from the baseband. The completed circuit exhibited wideband performance from 0.025 GHz to 2 GHz and IIP3 performance of -6.9 dBm in the high linearity mode. Finally, we designed a double noise-cancelling wideband receiver circuit by improving the performance of a wideband receiver with high immunity to blocker signals. In previous receivers, the LNTA was operated in two modes depending on the situation. In the improved receiver, the Gm ratio of the linearized LNTA was changed and the RF noise-cancelling technique was applied. The input matching and noise cancelling scheme introduced in the previous circuit was also applied and a wideband receiver circuit was designed to perform double noise-cancelling. As a result, the linearization and noise-cancellation of LNTA could be achieved at the same time, and the completed receiver circuit showed high IIP3 performance of 5 dBm with minimum noise figure of 1.4 dB. In conclusion, this thesis proposed a linearization technique for transconductor circuit and designed a wideband receiver based on current-mode receiver. The designed receiver circuit experimentally verified that it has low noise figure performance and high IIP3 performance and is tolerant to out-of-band blocker signals.Chapter 1. Introduction 1 1.1. Motivation of Wideband Receiver Architecture 2 1.2. Challenges in Designing Wideband Receiver 7 1.3. Prior Researches 13 1.3.1. N-Path Filter 14 1.3.2. Feed-Forward Blocker Filtering 16 1.3.3. Current-Mode Receiver 18 1.4. Research Objectives and Thesis Organization 22 Chapter 2. Transconductor Linearization Technique and Design of Tunable High-pass Filter 24 2.1. Transconductor Linearization Technique 27 2.2. Design of Tunable High-pass Filter 36 2.3. Measurement Results 41 2.4. Conclusions 46 Chapter 3. Wideband Noise-Cancelling Receiver Front-End Using Linearized Transconductor 47 3.1. Low-Noise Transconductance Amplifier Based on Linearized Transconductor 49 3.2. Wideband Noise-Cancelling Receiver Architecture 58 3.3. Measurement Results 64 3.4. Conclusions 70 Chapter 4. Blocker-Tolerant Wideband Double Noise-Cancelling Receiver Front-End 71 4.1. Linearized Noise-Cancelling Low-Noise Transconductance Amplifier 73 4.2. Wideband Double Noise-Cancelling Receiver Front-End 83 4.3. Measurement Results 90 4.4. Conclusions 97 Chapter 5. Conclusions 98 Bibliography 102 Abstract in Korean 112Docto

Automatic Tuning of Silicon Photonics Millimeter-Wave Transceivers Building Blocks

Today, continuously growing wireless traffic have guided the progress in the wireless communication systems. Now, evolution towards next generation (5G) wireless communication systems are actively researched to accommodate expanding future data traffic. As one of the most promising candidates, integrating photonic devices in to the existing wireless system is considered to improve the performance of the systems. Emerging silicon photonic integrated circuits lead this integration more practically, and open new possibilities to the future communication systems. In this dissertation, the development of the electrical wireless communication systems are briefly explained. Also, development of the microwave photonics and silicon photonics are described to understand the possibility of the hybrid SiP integrated wireless communication systems. A limitation of the current electrical wireless systems are addressed, and hybrid integrated mm-wave silicon photonic receiver, and silicon photonic beamforming transmitter are proposed and analyzed in system level. In the proposed mm-wave silicon photonic receiver has 4th order pole-zero silicon photonic filter in the system. Photonic devices are vulnerable to the process and temperature variations. It requires manual calibration, which is expensive, time consuming, and prone to human errors. Therefore, precise automatic calibration solution with modified silicon photonic filter structure is proposed and demonstrated. This dissertation demonstrates fully automatic tuning of silicon photonic all-pass filter (APF)-based pole/zero filters using a monitor-based tuning method that calibrates the initial response by controlling each pole and zero individually via micro-heaters. The proposed tuning approach calibrates severely degraded initial responses to the designed elliptic filter shapes and allows for automatic bandwidth and center frequency reconfiguration of these filters. This algorithm is demonstrated on 2nd- and 4th-order filters fabricated in a standard silicon photonics foundry process. After the initial calibration, only 300ms is required to reconfigure a filter to a different center frequency. Thermal crosstalk between the micro-heaters is investigated, with substrate thinning demonstrated to suppress this effect and reduce filter calibration to less than half of the original thick substrate times. This fully automatic tuning approach opens the possibility of employing silicon photonic filters in real communication systems. Also, in the proposed beamforming transmitter, true-time delay ring resonator based 1x4 beamforming network is imbedded. A proposed monitor-based tuning method compensates fabrication variations and thermal crosstalk by controlling micro-heaters individually using electrical monitors. The proposed tuning approach successfully demonstrated calibration of OBFN from severely degraded initial responses to well-defined group delay response required for the targeted radiating angle with a range of 60◦ (-30◦ to 30◦ ) in a linear beamforming antenna array. This algorithm is demonstrated on OBFN fabricated in a standard silicon photonics foundry process. The calibrated OBFN operates at 30GHz and provide 2GHz bandwidth. This fully automatic tuning approach opens the possibility of employing silicon OBFN in real wideband mm-wave wireless communication systems by providing robust operating solutions. All the proposed photonic circuits are implemented using the standard silicon photonic technologies, and resulted in several publications in IEEE/OSA Journals and Conferences

Dirty RF Signal Processing for Mitigation of Receiver Front-end Non-linearity

Moderne drahtlose Kommunikationssysteme stellen hohe und teilweise gegensätzliche Anforderungen an die Hardware der Funkmodule, wie z.B. niedriger Energieverbrauch, große Bandbreite und hohe Linearität. Die Gewährleistung einer ausreichenden Linearität ist, neben anderen analogen Parametern, eine Herausforderung im praktischen Design der Funkmodule. Der Fokus der Dissertation liegt auf breitbandigen HF-Frontends für Software-konfigurierbare Funkmodule, die seit einigen Jahren kommerziell verfügbar sind. Die praktischen Herausforderungen und Grenzen solcher flexiblen Funkmodule offenbaren sich vor allem im realen Experiment. Eines der Hauptprobleme ist die Sicherstellung einer ausreichenden analogen Performanz über einen weiten Frequenzbereich. Aus einer Vielzahl an analogen Störeffekten behandelt die Arbeit die Analyse und Minderung von Nichtlinearitäten in Empfängern mit direkt-umsetzender Architektur. Im Vordergrund stehen dabei Signalverarbeitungsstrategien zur Minderung nichtlinear verursachter Interferenz - ein Algorithmus, der besser unter "Dirty RF"-Techniken bekannt ist. Ein digitales Verfahren nach der Vorwärtskopplung wird durch intensive Simulationen, Messungen und Implementierung in realer Hardware verifiziert. Um die Lücken zwischen Theorie und praktischer Anwendbarkeit zu schließen und das Verfahren in reale Funkmodule zu integrieren, werden verschiedene Untersuchungen durchgeführt. Hierzu wird ein erweitertes Verhaltensmodell entwickelt, das die Struktur direkt-umsetzender Empfänger am besten nachbildet und damit alle Verzerrungen im HF- und Basisband erfasst. Darüber hinaus wird die Leistungsfähigkeit des Algorithmus unter realen Funkkanal-Bedingungen untersucht. Zusätzlich folgt die Vorstellung einer ressourceneffizienten Echtzeit-Implementierung des Verfahrens auf einem FPGA. Abschließend diskutiert die Arbeit verschiedene Anwendungsfelder, darunter spektrales Sensing, robuster GSM-Empfang und GSM-basiertes Passivradar. Es wird gezeigt, dass nichtlineare Verzerrungen erfolgreich in der digitalen Domäne gemindert werden können, wodurch die Bitfehlerrate gestörter modulierter Signale sinkt und der Anteil nichtlinear verursachter Interferenz minimiert wird. Schließlich kann durch das Verfahren die effektive Linearität des HF-Frontends stark erhöht werden. Damit wird der zuverlässige Betrieb eines einfachen Funkmoduls unter dem Einfluss der Empfängernichtlinearität möglich. Aufgrund des flexiblen Designs ist der Algorithmus für breitbandige Empfänger universal einsetzbar und ist nicht auf Software-konfigurierbare Funkmodule beschränkt.Today's wireless communication systems place high requirements on the radio's hardware that are largely mutually exclusive, such as low power consumption, wide bandwidth, and high linearity. Achieving a sufficient linearity, among other analogue characteristics, is a challenging issue in practical transceiver design. The focus of this thesis is on wideband receiver RF front-ends for software defined radio technology, which became commercially available in the recent years. Practical challenges and limitations are being revealed in real-world experiments with these radios. One of the main problems is to ensure a sufficient RF performance of the front-end over a wide bandwidth. The thesis covers the analysis and mitigation of receiver non-linearity of typical direct-conversion receiver architectures, among other RF impairments. The main focus is on DSP-based algorithms for mitigating non-linearly induced interference, an approach also known as "Dirty RF" signal processing techniques. The conceived digital feedforward mitigation algorithm is verified through extensive simulations, RF measurements, and implementation in real hardware. Various studies are carried out that bridge the gap between theory and practical applicability of this approach, especially with the aim of integrating that technique into real devices. To this end, an advanced baseband behavioural model is developed that matches to direct-conversion receiver architectures as close as possible, and thus considers all generated distortions at RF and baseband. In addition, the algorithm's performance is verified under challenging fading conditions. Moreover, the thesis presents a resource-efficient real-time implementation of the proposed solution on an FPGA. Finally, different use cases are covered in the thesis that includes spectrum monitoring or sensing, GSM downlink reception, and GSM-based passive radar. It is shown that non-linear distortions can be successfully mitigated at system level in the digital domain, thereby decreasing the bit error rate of distorted modulated signals and reducing the amount of non-linearly induced interference. Finally, the effective linearity of the front-end is increased substantially. Thus, the proper operation of a low-cost radio under presence of receiver non-linearity is possible. Due to the flexible design, the algorithm is generally applicable for wideband receivers and is not restricted to software defined radios

Design and characterization of downconversion mixers and the on-chip calibration techniques for monolithic direct conversion radio receivers

This thesis consists of eight publications and an overview of the research topic, which is also a summary of the work. The research described in this thesis is focused on the design of downconversion mixers and direct conversion radio receivers for UTRA/FDD WCDMA and GSM standards. The main interest of the work is in the 1-3 GHz frequency range and in the Silicon and Silicon-Germanium BiCMOS technologies. The RF front-end, and especially the mixer, limits the performance of direct conversion architecture. The most stringent problems are involved in the second-order distortion in mixers to which special attention has been given. The work introduces calibration techniques to overcome these problems. Some design considerations for front-end radio receivers are also given through a mixer-centric approach. The work summarizes the design of several downconversion mixers. Three of the implemented mixers are integrated as the downconversion stages of larger direct conversion receiver chips. One is realized together with the LNA as an RF front-end. Also, some stand-alone structures have been characterized. Two of the mixers that are integrated together with whole analog receivers include calibration structures to improve the second-order intermodulation rejection. A theoretical mismatch analysis of the second-order distortion in the mixers is also presented in this thesis. It gives a comprehensive illustration of the second-order distortion in mixers. It also gives the relationships between the dc-offsets and high IIP2. In addition, circuit and layout techniques to improve the LO-to-RF isolation are discussed. The presented work provides insight into how the mixer immunity against the second-order distortion can be improved. The implemented calibration structures show promising performance. On the basis of these results, several methods of detecting the distortion on-chip and the possibilities of integrating the automatic on-chip calibration procedures to produce a repeatable and well-predictable receiver IIP2 are presented.reviewe

Analog baseband circuits for WCDMA direct-conversion receivers

This thesis describes the design and implementation of analog baseband circuits for low-power single-chip WCDMA direct-conversion receivers. The reference radio system throughout the thesis is UTRA/FDD. The analog baseband circuit consists of two similar channels, which contain analog channel-select filters, programmable-gain amplifiers, and circuits that remove DC offsets. The direct-conversion architecture is described and the UTRA/FDD system characteristics are summarized. The UTRA/FDD specifications define the performance requirement for the whole receiver. Therefore, the specifications for the analog baseband circuit are obtained from the receiver requirements through calculations performed by hand. When the power dissipation of an UTRA/FDD direct-conversion receiver is minimized, the design parameters of an all-pole analog channel-select filter and the following Nyquist rate analog-to-digital converter must be considered simultaneously. In this thesis, it is shown that minimum power consumption is achieved with a fifth-order lowpass filter and a 15.36-MS/s Nyquist rate converter that has a 7- or 8-bit resolution. A fifth-order Chebyshev prototype with a passband ripple of 0.01 dB and a −3-dB frequency of 1.92-MHz is adopted in this thesis. The error-vector-magnitude can be significantly reduced by using a first-order 1.4-MHz allpass filter. The selected filter prototype fulfills all selectivity requirements in the analog domain. In this thesis, all the filter implementations use the opamp-RC technique to achieve insensitivity to parasitic capacitances and a high dynamic range. The adopted technique is analyzed in detail. The effect of the finite opamp unity-gain bandwidth on the filter frequency response can be compensated for by using passive methods. Compensation schemes that also track the process and temperature variations have been developed. The opamp-RC technique enables the implementation of low-voltage filters. The design and simulation results of a 1.5-V 2-MHz lowpass filter are discussed. The developed biasing scheme does not use any additional current to achieve the low-voltage operation, unlike the filter topology published previously elsewhere. Methods for removing DC offsets in UTRA/FDD direct-conversion receivers are presented. The minimum areas for cascaded AC couplings and DC-feedback loops are calculated. The distortion of the frequency response of a lowpass filter caused by a DC-feedback loop connected over the filter is calculated and a method for compensating for the distortion is developed. The time constant of an AC coupling can be increased using time-constant multipliers. This enables the implementation of AC couplings with a small silicon area. Novel time-constant multipliers suitable for systems that have a continuous reception, such as UTRA/FDD, are presented. The proposed time-constant multipliers only require one additional amplifier. In an UTRA/FDD direct-conversion receiver, the reception is continuous. In a low-power receiver, the programmable baseband gain must be changed during reception. This may produce large, slowly decaying transients that degrade the receiver performance. The thesis shows that AC-coupling networks and DC-feedback loops can be used to implement programmable-gain amplifiers, which do not produce significant transients when the gain is altered. The principles of operation, the design, and the practical implementation issues of these amplifiers are discussed. New PGA topologies suitable for continuously receiving systems have been developed. The behavior of these circuits in the presence of strong out-of-channel signals is analyzed. The interface between the downconversion mixers and the analog baseband circuit is discussed. The effect of the interface on the receiver noise figure and the trimming of mixer IIP2 are analyzed. The design and implementation of analog baseband circuits and channel-select filters for UTRA/FDD direct-conversion receivers are discussed in five application cases. The first case presents the analog baseband circuit for a chip-set receiver. A channel-select filter that has an improved dynamic range with a smaller supply current is presented next. The third and fifth application cases describe embedded analog baseband circuits for single-chip receivers. In the fifth case, the dual-mode analog baseband circuit of a quad-mode receiver designed for GSM900, DCS1800, PCS1900, and UTRA/FDD cellular systems is described. A new, highly linear low-power transconductor is presented in the fourth application case. The fourth application case also describes a channel-select filter. The filter achieves +99-dBV out-of-channel IIP2, +45-dBV out-of-channel IIP3 and 23-μVRMS input-referred noise with 2.6-mA current from a 2.7-V supply. In the fifth application case, a corresponding performance is achieved in UTRA/FDD mode. The out-of-channel IIP2 values of approximately +100 dBV achieved in this work are the best reported so far. This is also the case with the figure of merits for the analog channel-select filter and analog baseband circuit described in the fourth and fifth application cases, respectively. For equal power dissipation, bandwidth, and filter order, these circuits achieve approximately 10 dB and 15 dB higher spurious-free dynamic ranges, respectively, when compared to implementations that are published elsewhere and have the second best figure of merits.reviewe

SAW-Less Digitally-Assisted Receivers

Today’s wireless devices, like our smartphones, are able to handle multiple standards and bands for different applications, such as Bluetooth, Wi-Fi and data-voice communications. However, the cost of a modern transceiver is becoming mainly dominated by the large number of off-chip passive components, like Duplexers and SAW filters, needed to distinguish the desired signal among many interferences. Addressing the challenges that arise from the lack of RF filtering, a SAW-less architecture represents an interesting solution to reduce the platform complexity. This thesis proposes a feasible solution based on a SAW-less RF front-end able to meet the standard requirements and a digital system tailored to the RF path. The digital architecture, which represents the main topic of this thesis, is described in detail and experimentally tested to validate the proposed solutions