Analytical model of nanowire FETs in a partially ballistic or dissipative transport regime

The intermediate transport regime in nanoscale transistors between the fully ballistic case and the quasi equilibrium case described by the drift-diffusion model is still an open modeling issue. Analytical approaches to the problem have been proposed, based on the introduction of a backscattering coefficient, or numerical approaches consisting in the MonteCarlo solution of the Boltzmann transport equation or in the introduction of dissipation in quantum transport descriptions. In this paper we propose a very simple analytical model to seamlessly cover the whole range of transport regimes in generic quasi-one dimensional field-effect transistors, and apply it to silicon nanowire transistors. The model is based on describing a generic transistor as a chain of ballistic nanowire transistors in series, or as the series of a ballistic transistor and a drift-diffusion transistor operating in the triode region. As an additional result, we find a relation between the mobility and the mean free path, that has deep consequences on the understanding of transport in nanoscale devices

A Compact Model for the Ballistic Subthreshold Current in Ultra-Thin Independent Double-Gate MOSFETs

International audienceWe present an analytical model for the subthreshold characteristic of ultra-thin Independent Double-Gate (IDG) MOSFET working in the ballistic regime. This model takes into account short-channel effects, quantization effects and source-to-drain tunneling (WKB approximation) in the expression of the subthreshold drain current. Important device parameters, such as off-state current or subthreshold swing, can be easily evaluated through this full analytical approach. The model can be successfully implemented in a TCAD circuit simulator for the simulation of IDG MOSFET based-circuits

Devenlopment of Compact Small Signal Quasi Static Models for Multiple Gate Mosfets

En esta tesis hemos desarrollado los modelos compactos explícitos de carga y de capacitancia adaptados para los dispositivos dopados y no dopados de canal largo (DG MOSFETs dopados, DG MOSFETs no dopados, UTB MOSFETs no dopados y SGT no dopados) de un modelo unificado del control de carga derivado de la ecuación de Poisson. El esquema de modelado es similar en todos estos dispositivos y se adapta a cada geometría. Los modelos de la C.C. y de la carga son completamente compatibles. Las expresiones de la capacitancia se derivan del modelo de la carga. La corriente, la carga total y las capacitancias se escriben en términos de las densidades móviles de la carga en los extremos de fuente y drenador del canal. Las expresiones explícitas e infinitamente continuas se utilizan para las densidades móviles de la carga en la fuente y drenador. Las capacitancias modeladas demuestran el acuerdo excelente con las simulaciones numéricas 2D y 3D (SGT), en todos los regímenes de funcionamiento. Por lo tanto, el modelo es muy prometedor para ser utilizado en simuladores del circuito. Desafortunadamente, no mucho trabajo se ha dedicado a este dominio de modelado. Las cargas analíticas y las capacitancias, asociadas a cada terminal se prefieren en la simulación de circuito. Con respecto al SGT MOSFET, nuestro grupo fue el primero en desarrollar y publicar un modelo de las cargas y de las capacitancias intrínsecas, que es también analítico y explícito. La tesis es organizada como sigue: el capítulo (1) presenta el estado del arte, capítulo (2) el modelado compacto de los cuatro dispositivos: DG MOSFETs dopados, DG MOSFETs no dopados, UTB MOSFETs no dopados y SGT no dopados; en el capítulo (3) estudiamos las capacitancias de fricción en MuGFETs. Finalmente el capítulo (4) resuma el trabajo hecho y los futuros objetivos que necesitan ser estudiados. Debido a la limitación de los dispositivos optimizados disponibles para el análisis, la simulación numérica fue utilizada como la herramienta principal del análisis. Sin embargo, cuando estaban disponibles, medidas experimentales fueron utilizadas para validar nuestros resultados. Por ejemplo, en la sección 2A, en el caso de DG MOSFETs altamente dopados podríamos comparar nuestros resultados con datos experimentales de FinFETs modelados como DG MOSFETs. La ventaja principal de este trabajo es el carácter analítico y explícito del modelo de la carga y de la capacitancia que las hace fácil de implementar en simuladores de circuitos. El modelo presenta los resultados casi perfectos para diversos casos del dopaje y para diversas estructuras no clásicas del MOSFET (los DG MOSFETs, los UTB MOSFETs y los SGTs). La variedad de las estructuras del MOSFET en las cuales se ha incluido nuestro esquema de modelado y los resultados obtenidos, demuestran su validez absoluta. En el capítulo 3, investigamos la influencia de los parámetros geométricos en el funcionamiento en RF de los MuGFETs. Demostramos el impacto de parámetros geométricos importantes tales como el grosor de la fuente y del drenador o, el espaciamiento de las fins, la anchura del espaciador, etc. en el componente parásito de la capacitancia de fricción de los transistores de la múltiple-puerta (MuGFET). Los resultados destacan la ventaja de disminuir el espaciamiento entre las fins para MuGFETs y la compensación entre la reducción de las resistencias parásitas de fuente y drenador y el aumento de capacitancias de fricción cuando se introduce la tecnología del crecimiento selectivo epitaxial (SEG). La meta de nuestro estudio y trabajo es el uso de nuestros modelos en simuladores de circuitos. El grupo de profesor Aranda, de la Universidad de Granada ha puesto el modelo actual de SGT en ejecución en el simulador Agilent ADS y buenos resultados fueron obtenidos.In this thesis we have developed explicit compact charge and capacitance models adapted for doped and undoped long-channel devices (doped Double-Gate (DG) MOSFETs, undoped DG MOSFETs, undoped Ultra-Thin-Body (UTB) MOSFETs and undoped Surrounding Gate Transistor (SGT)) from a unified charge control model derived from Poisson's equation. The modelling scheme is similar in all these devices and is adapted to each geometry. The dc and charge models are fully compatible. The capacitance expressions are derived from the charge model. The current, total charges and capacitances are written in terms of the mobile charge sheet densities at the source and drain ends of the channel. Explicit and infinitely continuous expressions are used for the mobile charge sheet densities at source and drain. As a result, all small signal parameters will have an infinite order of continuity. The modeled capacitances show excellent agreement with the 2D and 3D (SGT) numerical simulations, in all operating regimes. Therefore, the model is very promising for being used in circuit simulators. Unfortunately, not so much work has been dedicated to this modelling domain. Analytical charges and capacitances, associated with each terminal are preferred in circuit simulation. Regarding the surrounding-gate MOSFET, our group was the first to develop and publish a model of the charges and intrinsic capacitances, which is also analytic and explicit. The thesis is organized as follows: Chapter (1) presents the state of the art, Chapter (2) the compact modeling of the four devices: doped DG MOSFETs, undoped DG MOSFETs, undoped UTB MOSFETs and undoped SGT; in Chapter (3) we study the fringing capacitances in MuGFETs. Finally Chapter (4) summarizes the work done and the future points that need to be studied. Due to the limitation of available optimized devices for analysis, numerical simulation was used as the main analysis tool. However, when available, measurements were used to validate our results. The experimental part was realised at the Microelectronics Laboratory, Université Catholique de Louvain, Louvain-la Neuve, Belgium. For example, in section 2A, in the case of highly-doped DG MOSFETs we could compare our results with experimental data from FinFETs modeled as DG MOSFETs. The main advantage of this work is the analytical and explicit character of the charge and capacitance model that makes it easy to implement in circuit simulators. The model presents almost perfect results for different cases of doping (doped/undoped devices) and for different non classical MOSFET structures (DG MOSFET, UTB MOSFETs and SGT). The variety of the MOSFET structures in which our modeling scheme has been included and the obtained results, demonstrate its absolute validity. In chapter 3, we investigate the influence of geometrical parameters on the RF performance in MuGFETs. We show the impact of important geometrical parameters such as source and drain thickness, fin spacing, spacer width, etc. on the parasitic fringing capacitance component of multiple-gate field-effect transistors (MuGFET). Results highlight the advantage of diminishing the spacing between fins for MuGFETs and the trade-off between the reduction of parasitic source and drain resistances and the increase of fringing capacitances when Selective Epitaxial Growth (SEG) technology is introduced. The goal of our study and work is the usage of our models in circuit simulators. This part, of implementing and testing our models of these multi gate MOSFET devices in circuit simulators has already begun. The group of Professor Aranda, from the University of Granada has implemented the SGT current model in the circuit simulator Agilent ADS and good results were obtained

Modeling and Simulation of Negative Capacitance MOSFETs

The current and voltage characteristics of a MOSFET device are maily characterized by the source to channel barrier which is controlled by the gate voltage. The Boltazmann statistics which govern the number of carriers that are able to cross the barrier indicates that to increase the current by a decade, atleast 60 mV of rise in gate voltage is required. As a result of this limitation, the threshold voltage of modern MOSFETs cannot be less than about 0.3 V for an ION to IOFF ratio of 5 decades. This has put a fundamental bottleneck in voltage downscaling increasing the power consumption in modern IC based chips with billions of transistors. Sayeef Salahuddin and Supriyo Dutta proposed the idea of including ferroelectric in MOSFET gate stack which allows an internal voltage ampli�cation at the MOSFET channel which can be used to achieve a smaller subthreshold swing which would further reduce the power consumption of the devices. In this thesis we have undertaken a simulation based study of such devices to study how the inclusion of negative capacitance ferroelectrics leads changes in various device characteristics. Initially we have taken a compact modeling based approach to study device characteristics in latest industry standard FinFET devices. For this purpose we have used the BSIM-CMG Verilog A model and modi�ed the model appropriately to include the e�ect of negative capacitance ferroelectric in the gate stack. This simulation allowed us to observe that negative capacitance (NC) devices can indeed give a subthreshold swing lesser than 60 mV/dec. Further other interesting properties like negative output resistance and drain induced barrier rising are observed. Using the compact models developed above, we have analyzed some simple circuits with NC devices. Initially an inverter shows a hysteresis in the transfer characteristics. This can be attributed to negative di�erential resistance. Ring oscillator analysis shows that RO frequency for NC devices is lesser than that of regular devices due to enhanced gate capacitance and slower response of ferroelectrics. Scaling analysis has been performed to see the performance of NC devices in future technologies. For this we used TCAD analysis coupled with Landau Khalatnikov equation. This analysis shows that NC devices are more e�ective in suppressing short channel e�ects like DIBL and can hence be used for further downscaling of the devices. Finally we develop models to take into account the multidomain Landau equations for ferroelec- tric into account. We have performed such an analysis for a ferroelectric resistor series network. A similar analysis is performed for short channel double gate MOSFET without inter layer metal be- tween ferroelectric and the internal MOS device. This analysis showed that coupling factor between ferroelectric domains plays an important role in the device characteristics

Compact modeling of gate tunneling leakage current in advanced nanoscale soi mosfets

En esta tesis se han desarrollado modelos compactos de corriente de fuga por túnel de puerta en SOI MOSFET (de simple y doble puerta) avanzados basados en una aproximación WKB de la probabilidad de túnel. Se han estudiado los materiales dieléctricos high-k más prometedores para los diferentes requisitos de nodos tecnológicos de acuerdo ala hoja de ruta ITRS de miniaturización de dispositivos electrónicos. Hemos presentado un modelo compacto de particionamiento de la corriente de fuga de puerta para un MOSFET nanométrico de doble puerta (DG MOSFET), utilizando modelos analíticos de la corriente de fuga por el túnel directo de puerta. Se desarrollaron también Los modelos analíticos dependientes de la temperatura de la corriente de túnel en la región de inversión y de la corriente túnel asistido por trampas en régimen subumbral. Finalmente, se desarrolló una técnica de extracción automática de parámetros de nuestro modelo compacto en DG MOSFET incluyendo efectos de canal corto. La corriente de la puerta por túnel directo y asistido por trampas modelada mediante los parámetros extraídos se verificó exitosamente mediante comparación con medidas experimentales

Simulation of charge-trapping in nano-scale MOSFETs in the presence of random-dopants-induced variability

The growing variability of electrical characteristics is a major issue associated with continuous downscaling of contemporary bulk MOSFETs. In addition, the operating conditions brought about by these same scaling trends have pushed MOSFET degradation mechanisms such as Bias Temperature Instability (BTI) to the forefront as a critical reliability threat. This thesis investigates the impact of this ageing phenomena, in conjunction with device variability, on key MOSFET electrical parameters. A three-dimensional drift-diffusion approximation is adopted as the simulation approach in this work, with random dopant fluctuations—the dominant source of statistical variability—included in the simulations. The testbed device is a realistic 35 nm physical gate length n-channel conventional bulk MOSFET. 1000 microscopically different implementations of the transistor are simulated and subjected to charge-trapping at the oxide interface. The statistical simulations reveal relatively rare but very large threshold voltage shifts, with magnitudes over 3 times than that predicted by the conventional theoretical approach. The physical origin of this effect is investigated in terms of the electrostatic influences of the random dopants and trapped charges on the channel electron concentration. Simulations with progressively increased trapped charge densities—emulating the characteristic condition of BTI degradation—result in further variability of the threshold voltage distribution. Weak correlations of the order of 10-2 are found between the pre-degradation threshold voltage and post-degradation threshold voltage shift distributions. The importance of accounting for random dopant fluctuations in the simulations is emphasised in order to obtain qualitative agreement between simulation results and published experimental measurements. Finally, the information gained from these device-level physical simulations is integrated into statistical compact models, making the information available to circuit designers

Investigation of the RTN Distribution of nanoscale MOS devices from subthreshold to on-state

This letter presents a numerical investigation of the statistical distribution of the random telegraph noise (RTN) amplitude in nanoscale MOS devices, focusing on the change of its main features when moving from the subthreshold to the on-state conduction regime. Results show that while the distribution can be well approximated by an exponential behavior in subthreshold, large deviations from this behavior appear when moving toward the on-state regime, despite a low probability exponential tail at high RTN amplitudes being preserved. The average value of the distribution is shown to keep an inverse proportionality to channel area, while the slope of the high-amplitude exponential tail changes its dependence on device width, length, and doping when moving from subthreshold to on-state