Extended class of linear feedback shift registers

Shift registers with linear feedback are frequently used. They owe their popularity to very well developed theoretical base. Registers with feedback of prime polynomials are of particular practical importance. They are willingly applied as test sequence generators and test response compactors. The article presents an attempt to extend the class of registers with linear feedback. Basing on the formal description of the register, the algorithms of register transformation are proposed. It allows to obtain the registers with equivalent graphs.[1] I. Gosciniak, “Linear Registers with Mixed Feedback, in Polish; Rejestry liniowe z mieszanym sprzȩżeniem zwrotnym,” Pomiary Automatyka Kontrola, no. 1, pp. 4–6, 1996.[2] K. Iwasaki, “Analysis and proposal of signature circuits for LSI testing,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 7, no. 1, pp. 84–90, 1988.[3] L.-T. Wang, N. Touba, R. Brent, H. Xu, and H. Wang, “On Designing Transformed Linear Feedback Shift Registers with Minimum Hardware Cost – Technical Report,” Computer Engineering Research Center Department of Electrical & Computer Engineering The University of Texas at Austin, 2011.[4] J. Rajski, J. Tyszer, M. Kassab, and N. Mukherjee, “Method for Synthesizing Linear Finite State Machines,” U.S. Patent, No. 6,353,842, 2002.[5] I. Gosciniak, “Equivalent Form of Linear Feedback Shift Registers,” in XIXth National Conference Circuit Theory and Eletronic Networks, 1996, pp. 115–120.[6] L. Alaus, D. Noguet, and J. Palicot, “A Reconfigurable LFSR for Tristandard SDR Transceiver, Architecture and Complexity Analysis,” in Digital System Design Architectures, Methods and Tools, 2008. DSD ’08. 11th EUROMICRO Conference on. IEEE Computer Society, 2008, pp. 61–67.[7] R. Ash, Information Theory. John Wiley & Sons, 1967.[8] M. Kopec, “Can Nonlinear Compactors Be Better than Linear Ones?” IEEE Trans. Comput., no. 11, pp. 1275–1282, 1995.[9] A. Gucha and L. Kinney, “Relating the Cyclic Behaviour of Linear Intrainverted Feedback shift Registers,” IEEE Transactions on Computers, vol. 41, no. 9, pp. 1088–1100, 1992

Design of software radio

Software Define Radio (SDR) has become a prevalent technology in wireless systems. In SDR some or all of the signal specific handling is implemented in software functions, while other functions like decimation, interpolation, digital up-conversion and digital down conversion are done on reprogrammable Digital Signal Processor or Field Programmable Gate Arrays.Twelve laboratory exercises have been designed to lead the student through the process of using the Universal Software Radio peripheral (USRP) hardware and GNU Radio open source software

Design of software radio

Software Define Radio (SDR) has become a prevalent technology in wireless systems. In SDR some or all of the signal specific handling is implemented in software functions, while other functions like decimation, interpolation, digital up-conversion and digital down conversion are done on reprogrammable Digital Signal Processor or Field Programmable Gate Arrays.Twelve laboratory exercises have been designed to lead the student through the process of using the Universal Software Radio peripheral (USRP) hardware and GNU Radio open source software

RHINO software-defined radio processing blocks

This MSc project focuses on the design and implementation of a library of parameterizable, modular and reusable Digital IP blocks designed around use in Software-Defined Radio (SDR) applications and compatibility with the RHINO platform. The RHINO platform has commonalities with the better known ROACH platform, but it is a significantly cut-down and lowercost alternative which has similarities in the interfacing and FPGA/Processor interconnects of ROACH. The purpose of the library and design framework presented in this work aims to alleviate some of the commercial, high cost and static structure concerns about IP cores provided by FPGA manufactures and third-party IP vendors. It will also work around the lack of parameters and bus compatibility issues often encountered when using the freely available open resources. The RHINO hardware platform will be used for running practical applications and testing of the blocks. The HDL library that is being constructed is targeted towards both novice and experienced low-level HDL developers who can download and use it for free, and it will provide them experience of using IP Cores that support open bus interfaces in order to exploit SoC design without commercial, parameter and bus compatibility limitations. The provided modules will be of particularly benefit to the novice developers in providing ready-made examples of processing blocks, as well as parameterization settings for the interfacing blocks and associated RF receiver side configuration settings; all together these examples will help new developers establish effective ways to build their own SDR prototypes using RHINO

Designing Flexible, Energy Efficient and Secure Wireless Solutions for the Internet of Things

The Internet of Things (IoT) is an emerging concept where ubiquitous physical objects (things) consisting of sensor, transceiver, processing hardware and software are interconnected via the Internet. The information collected by individual IoT nodes is shared among other often heterogeneous devices and over the Internet. This dissertation presents flexible, energy efficient and secure wireless solutions in the IoT application domain. System design and architecture designs are discussed envisioning a near-future world where wireless communication among heterogeneous IoT devices are seamlessly enabled. Firstly, an energy-autonomous wireless communication system for ultra-small, ultra-low power IoT platforms is presented. To achieve orders of magnitude energy efficiency improvement, a comprehensive system-level framework that jointly optimizes various system parameters is developed. A new synchronization protocol and modulation schemes are specified for energy-scarce ultra-small IoT nodes. The dynamic link adaptation is proposed to guarantee the ultra-small node to always operate in the most energy efficiency mode, given an operating scenario. The outcome is a truly energy-optimized wireless communication system to enable various new applications such as implanted smart-dust devices. Secondly, a configurable Software Defined Radio (SDR) baseband processor is designed and shown to be an efficient platform on which to execute several IoT wireless standards. It is a custom SIMD execution model coupled with a scalar unit and several architectural optimizations: streaming registers, variable bitwidth, dedicated ALUs, and an optimized reduction network. Voltage scaling and clock gating are employed to further reduce the power, with a more than a 100% time margin reserved for reliable operation in the near-threshold region. Two upper bound systems are evaluated. A comprehensive power/area estimation indicates that the overhead of realizing SDR flexibility is insignificant. The benefit of baseband SDR is quantified and evaluated. To further augment the benefits of a flexible baseband solution and to address the security issue of IoT connectivity, a light-weight Galois Field (GF) processor is proposed. This processor enables both energy-efficient block coding and symmetric/asymmetric cryptography kernel processing for a wide range of GF sizes (2^m, m = 2, 3, ..., 233) and arbitrary irreducible polynomials. Program directed connections among primitive GF arithmetic units enable dynamically configured parallelism to efficiently perform either four-way SIMD GF operations, including multiplicative inverse, or a long bit-width GF product in a single cycle. This demonstrates the feasibility of a unified architecture to enable error correction coding flexibility and secure wireless communication in the low power IoT domain.PHDComputer Science & EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/137164/1/yajchen_1.pd

GPS system implementation using software defined radio platform

Every day new technologies are being developed and introduced to the market, shaping people's daily life. The principal aim of our society is making up an ecosystem that provides anything, anytime, anywhere. For this purpose, more powerful and efficient devices, improved devices are being designed as the key ingredients. In this report it is shown the study and the implementation of a Global Positioning Service device, a technology that is used by more than four thousand millions of users. The present work explores the Global Positioning System development using a Software Radio Defined Platform. The implementation of this development is divided into four main parts: GPS signal acquisition and treatment carried out by the receptor, GPS received signal demodulation using Binary Phase Shift Keying, decoding through Direct Sequence Spread Spectrum of the previous demodulated signal, and finally, once the necessary data from the message was obtained, the position estimation. In order to perform all the process it was used as working tool a device known as Universal Software Radio Peripheral. This device allows for analysing from a visual point of view more accurate the four different phases explained previously. These phases represent the basis to be able to achieve the necessary knowledge about proper operation ot the Global Positioning System. The whole application was developd using LabVIEW software, a data ow visual programming language and environment designed by National Instruments.Cada día nuevas tecnologías son desarrolladas e introducidas en el mercado, modelando así la vida diaria de la sociedad. El principal objetivo de nuestra sociedad es conseguir crear un ecosistema que proporcione lo que sea necesario, en cualquier momento y en cualquier lugar. Para ello, equipos más potentes, eficientes y mejorados son diseñados como los ingredientes claves de este nuevo ecosistema. En este trabajo se presenta el estudio y la implementación de un receptor de señales GPS, tecnología que hoy en día es utilizada por más de cuatro mil millones de usuarios. Para ello se lleva a cabo el desarrollo del Sistema de Posicionamiento Global (GPS) mediante la utilización de una plataforma de radio definida por software. La implementación del desarrollo se divide en cuatro procesos principales: adquisición y el tratamiento de la señal GPS por parte del receptor, demodulación por desplazamiento de fase binaria (BPSK) de la señal GPS recibida, decodificación en espectro ensanchado por secuencia directa (DSSS) de la señal demodulada y por último, una vez obtenidos los datos necesarios del mensaje, la estimación de la posición. Para la realización de todo el proceso se utilizó como herramienta de trabajo un dispositivo conocido como Universal Software Radio Peripheral (USRP). Este aparato permite analizar desde un punto de vista visual más preciso las cuatro fases indicadas anteriormente. Estas fases suponen la base para lograr adquirir el conocimiento necesario sobre el funcionamiento del Sistema de Posicionamiento Global (GPS). El desarrollo completo de la aplicación fue implementado utilizando LabVIEW, un entorno de desarrollo integrado diseñado por la conocida compañía National Instruments.Ingeniería en Tecnologías de Telecomunicació

Implementação de Tx/Rx banda base para 802.11-2007 em FPGA

Mestrado em Engenharia Electrónica e TelecomunicaçõesO trabalho apresentado nesta dissertação teve como objectivo o desenvolvimento da camada física de um sistema de transmissão e recepção de sinais OFDM baseados no standard IEEE 802.11-2007. O sistema desenvolvido inclui geração de dados aleatórios, modulador QAM, inserção de pilotos e subportadora DC, IFFT com adição de Prefixo Cíclico, buffer de saída e o consequente oposto para o receptor. A dissertação encontra-se dividida em duas partes principais. Na primeira parte, o sistema foi projectado e simulado em Matlab através do ambiente Simulink com o auxílio dos blocos da Xilinx inseridos no seu software System Generator for DSP. Na segunda parte, foram adicionadas DACʼs ao transmissor e o próprio foi compilado para um bloco e testado no XtremeDSP Development Kit-IV da Nallatech que inclui uma Field-Programmable Gate Array. Todos os módulos foram desenhados usando os blocos do System Generator for DSP da Xilinx. O kit está conectado ao computador através de uma interface PCI. Os dados obtidos são exibidos em Matlab para a primeira parte e num osciloscópio para a segunda parte.It was the objective of this dissertation the development of the Physical Layer of an IEEE 802.11-2007 Transmitter-Receiver system for generating OFDM signals. The developed design includes random Data Generation, QAM Modulator, Pilots and DC subcarrier insertion, IFFT with Cyclic Prefix insertion, an Output Buffer and the subsequent opposite for its receiver. This dissertation was divided in two main segments. In the first segment, the system was designed and simulated in Matlab through the Simulink environment using Xilinxʼs System Generator for DSP blocks. In the second part, DACʼs where added to the transmitter in order to compile it into a single block and test it on Nallatechʼs XtremeDSP Development Kit-IV, which includes a Field-Programmable Gate Array. All modules were designed using Xilinxʼs System Generator for DSP blocks. The kit is connected to the computer through a PCI interface. Output data is displayed on the Matlab environment for part one and on an oscilloscope for part two

Efficient FPGA implementation and power modelling of image and signal processing IP cores

This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.Field Programmable Gate Arrays (FPGAs) are the technology of choice in a number ofimage and signal processing application areas such as consumer electronics, instrumentation, medical data processing and avionics due to their reasonable energy consumption, high performance, security, low design-turnaround time and reconfigurability. Low power FPGA devices are also emerging as competitive solutions for mobile and thermally constrained platforms. Most computationally intensive image and signal processing algorithms also consume a lot of power leading to a number of issues including reduced mobility, reliability concerns and increased design cost among others. Power dissipation has become one of the most important challenges, particularly for FPGAs. Addressing this problem requires optimisation and awareness at all levels in the design flow. The key achievements of the work presented in this thesis are summarised here. Behavioural level optimisation strategies have been used for implementing matrix product and inner product through the use of mathematical techniques such as Distributed Arithmetic (DA) and its variations including offset binary coding, sparse factorisation and novel vector level transformations. Applications to test the impact of these algorithmic and arithmetic transformations include the fast Hadamard/Walsh transforms and Gaussian mixture models. Complete design space exploration has been performed on these cores, and where appropriate, they have been shown to clearly outperform comparable existing implementations. At the architectural level, strategies such as parallelism, pipelining and systolisation have been successfully applied for the design and optimisation of a number of cores including colour space conversion, finite Radon transform, finite ridgelet transform and circular convolution. A pioneering study into the influence of supply voltage scaling for FPGA based designs, used in conjunction with performance enhancing strategies such as parallelism and pipelining has been performed. Initial results are very promising and indicated significant potential for future research in this area. A key contribution of this work includes the development of a novel high level power macromodelling technique for design space exploration and characterisation of custom IP cores for FPGAs, called Functional Level Power Analysis and Modelling (FLPAM). FLPAM is scalable, platform independent and compares favourably with existing approaches. A hybrid, top-down design flow paradigm integrating FLPAM with commercially available design tools for systematic optimisation of IP cores has also been developed

Digital ADCs and ultra-wideband RF circuits for energy constrained wireless applications by Denis Clarke Daly.

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.Cataloged from PDF version of thesis.Includes bibliographical references (p. 173-183).Ongoing advances in semiconductor technology have enabled a multitude of portable, low power devices like cellular phones and wireless sensors. Most recently, as transistor device geometries reach the nanometer scale, transistor characteristics have changed so dramatically that many traditional circuits and architectures are no longer optimal and/or feasible. As a solution, much research has focused on developing 'highly digital' circuits and architectures that are tolerant of the increased leakage, variation and degraded voltage headrooms associated with advanced CMOS processes. This thesis presents several highly digital, mixed-signal circuits and architectures designed for energy constrained wireless applications. First, as a case study, a highly digital, voltage scalable flash ADC is presented. The flash ADC, implemented in 0.18 [mu]m CMOS, leverages redundancy and calibration to achieve robust operation at supply voltages from 0.2 V to 0.9 V. Next, the thesis expands in scope to describe a pulsed, noncoherent ultra-wideband transceiver chipset, implemented in 90 nm CMOS and operating in the 3-to-5 GHz band. The all-digital transmitter employs capacitive combining and pulse shaping in the power amplifier to meet the FCC spectral mask without any off-chip filters. The noncoherent receiver system-on-chip achieves both energy efficiency and high performance by employing simple amplifier and ADC structures combined with extensive digital calibration. Finally, the transceiver chipset is integrated in a complete system for wireless insect flight control.(cont.) Through the use of a flexible PCB and 3D die stacking, the total weight of the electronics is kept to 1 g, within the carrying capacity of an adult Manduca sexta moth. Preliminary wireless flight control of a moth in a wind tunnel is demonstrated.Ph.D

Efficient FPGA implementation and power modelling of image and signal processing IP cores

Field Programmable Gate Arrays (FPGAs) are the technology of choice in a number ofimage and signal processing application areas such as consumer electronics, instrumentation, medical data processing and avionics due to their reasonable energy consumption, high performance, security, low design-turnaround time and reconfigurability. Low power FPGA devices are also emerging as competitive solutions for mobile and thermally constrained platforms. Most computationally intensive image and signal processing algorithms also consume a lot of power leading to a number of issues including reduced mobility, reliability concerns and increased design cost among others. Power dissipation has become one of the most important challenges, particularly for FPGAs. Addressing this problem requires optimisation and awareness at all levels in the design flow. The key achievements of the work presented in this thesis are summarised here. Behavioural level optimisation strategies have been used for implementing matrix product and inner product through the use of mathematical techniques such as Distributed Arithmetic (DA) and its variations including offset binary coding, sparse factorisation and novel vector level transformations. Applications to test the impact of these algorithmic and arithmetic transformations include the fast Hadamard/Walsh transforms and Gaussian mixture models. Complete design space exploration has been performed on these cores, and where appropriate, they have been shown to clearly outperform comparable existing implementations. At the architectural level, strategies such as parallelism, pipelining and systolisation have been successfully applied for the design and optimisation of a number of cores including colour space conversion, finite Radon transform, finite ridgelet transform and circular convolution. A pioneering study into the influence of supply voltage scaling for FPGA based designs, used in conjunction with performance enhancing strategies such as parallelism and pipelining has been performed. Initial results are very promising and indicated significant potential for future research in this area. A key contribution of this work includes the development of a novel high level power macromodelling technique for design space exploration and characterisation of custom IP cores for FPGAs, called Functional Level Power Analysis and Modelling (FLPAM). FLPAM is scalable, platform independent and compares favourably with existing approaches. A hybrid, top-down design flow paradigm integrating FLPAM with commercially available design tools for systematic optimisation of IP cores has also been developed.EThOS - Electronic Theses Online ServiceGBUnited Kingdo