A CMOS Q-Enhancement Bandpass-Filter For Use In Paging Receivers

Paging receivers often have to work in a dense\ud signal environment. This poses high demands on the preselection\ud filter. One of the most difficult aspects is the large\ud image rejection demand, which only can be satisfied by use\ud of a narrow-band or high-Q filter. The practical restrictions\ud for possible filter implementations are the low cost, low\ud power and the small size of the pager. By use of positive feedback\ud around a cheap off-chip low-Q inductor we obtain an\ud enhanced quality factor. We are therefore able to construct\ud selective filters using cheap small-size inductors. The price\ud paid for Q-enhancement is a larger noise and higher sensitivity\ud to component variations. The higher noise influence\ud is eliminated using a high gain in the preceding LNA-stage,\ud which is considered a part of the filter. Simulated results\ud are: Q enhanced from 30 to 100, Image-rejection = 48dB,\ud f0 = 280MHz, Voltage-gain = 20dB, Noise- figure = 2.4dB,\ud IMFDR = 66dB, IDD = 1mA, VDD = 2V. The original contribution\ud of this work is the application of the enhancement\ud principle to off-chip components, which benefits the minimization\ud of size and cost

Tunable n-path notch filters for blocker suppression: modeling and verification

N-path switched-RC circuits can realize filters with very high linearity and compression point while they are tunable by a clock frequency. In this paper, both differential and single-ended N-path notch filters are modeled and analyzed. Closed-form equations provide design equations for the main filtering characteristics and nonidealities such as: harmonic mixing, switch resistance, mismatch and phase imbalance, clock rise and fall times, noise, and insertion loss. Both an eight-path single-ended and differential notch filter are implemented in 65-nm CMOS technology. The notch center frequency, which is determined by the switching frequency, is tunable from 0.1 to 1.2 GHz. In a 50- environment, the N-path filters provide power matching in the passband with an insertion loss of 1.4–2.8 dB. The rejection at the notch frequency is 21–24 dB,P1 db> + 2 dBm, and IIP3 > + 17 dBm

Tunable C Band Coupled-C BPF with Resonators using Active Capacitor and Inductor

In this thesis, a classic second-order coupled-capacitor Chebyshev bandpass filter with resonators using active capacitor and inductor is presented. The low cost and small size of CMOS active components makes the band pass filter (BPF) attractive in fully-integrated CMOS applications. The active capacitor is designed to compensate active inductor\u27s resistance for resistive match in the resonator. Meanwhile, adjusting design parameter of the active component provides BPF tunability in center frequency, pass band and pass band gain. Designed in 1.8V 180 nanometer CMOS process, the BPF has a tuning frequency range of 758-864 MHz, a controllable pass band of 7.1-65.9 MHz, a Q factor of 12-107, a pass band gain of 6.5-18.1dB and a stopband rejection of 38-50 dB

Saw-Less radio receivers in CMOS

Smartphones play an essential role in our daily life. Connected to the internet, we can easily keep in touch with family and friends, even if far away, while ever more apps serve us in numerous ways. To support all of this, higher data rates are needed for ever more wireless users, leading to a very crowded radio frequency spectrum. To achieve high spectrum efficiency while reducing unwanted interference, high-quality band-pass filters are needed. Piezo-electrical Surface Acoustic Wave (SAW) filters are conventionally used for this purpose, but such filters need a dedicated design for each new band, are relatively bulky and also costly compared to integrated circuit chips. Instead, we would like to integrate the filters as part of the entire wireless transceiver with digital smartphone hardware on CMOS chips. The research described in this thesis targets this goal. It has recently been shown that N-path filters based on passive switched-RC circuits can realize high-quality band-select filters on CMOS chips, where the center frequency of the filter is widely tunable by the switching-frequency. As CMOS downscaling following Moore’s law brings us lower clock-switching power, lower switch on-resistance and more compact metal-to-metal capacitors, N-path filters look promising. This thesis targets SAW-less wireless receiver design, exploiting N-path filters. As SAW-filters are extremely linear and selective, it is very challenging to approximate this performance with CMOS N-path filters. The research in this thesis proposes and explores several techniques for extending the linearity and enhancing the selectivity of N-path switched-RC filters and mixers, and explores their application in CMOS receiver chip designs. First the state-of-the-art in N-path filters and mixer-first receivers is reviewed. The requirements on the main receiver path are examined in case SAW-filters are removed or replaced by wideband circulators. The feasibility of a SAW-less Frequency Division Duplex (FDD) radio receiver is explored, targeting extreme linearity and compression Irequirements. A bottom-plate mixing technique with switch sharing is proposed. It improves linearity by keeping both the gate-source and gate-drain voltage swing of the MOSFET-switches rather constant, while halving the switch resistance to reduce voltage swings. A new N-path switch-RC filter stage with floating capacitors and bottom-plate mixer-switches is proposed to achieve very high linearity and a second-order voltage-domain RF-bandpass filter around the LO frequency. Extra out-of-band (OOB) rejection is implemented combined with V-I conversion and zero-IF frequency down-conversion in a second cross-coupled switch-RC N-path stage. It offers a low-ohmic high-linearity current path for out-of-band interferers. A prototype chip fabricated in a 28 nm CMOS technology achieves an in-band IIP3 of +10 dBm , IIP2 of +42 dBm, out-of-band IIP3 of +44 dBm, IIP2 of +90 dBm and blocker 1-dB gain-compression point of +13 dBm for a blocker frequency offset of 80 MHz. At this offset frequency, the measured desensitization is only 0.6 dB for a 0-dBm blocker, and 3.5 dB for a 10-dBm blocker at 0.7 GHz operating frequency (i.e. 6 and 9 dB blocker noise figure). The chip consumes 38-96 mW for operating frequencies of 0.1-2 GHz and occupies an active area of 0.49 mm2. Next, targeting to cover all frequency bands up to 6 GHz and achieving a noise figure lower than 3 dB, a mixer-first receiver with enhanced selectivity and high dynamic range is proposed. Capacitive negative feedback across the baseband amplifier serves as a blocker bypassing path, while an extra capacitive positive feedback path offers further blocker rejection. This combination of feedback paths synthesizes a complex pole pair at the input of the baseband amplifier, which is up-converted to the RF port to obtain steeper RF-bandpass filter roll-off than the conventional up-converted real pole and reduced distortion. This thesis explains the circuit principle and analyzes receiver performance. A prototype chip fabricated in 45 nm Partially Depleted Silicon on Insulator (PDSOI) technology achieves high linearity (in-band IIP3 of +3 dBm, IIP2 of +56 dBm, out-of-band IIP3 = +39 dBm, IIP2 = +88 dB) combined with sub-3 dB noise figure. Desensitization due to a 0-dBm blocker is only 2.2 dB at 1.4 GHz operating frequency. IIFinally, to demonstrate the performance of the implemented blocker-tolerant receiver chip designs, a test setup with a real mobile phone is built to verify the sensitivity of the receiver chip for different practical blocking scenarios

An Accurate Automatic Quality-Factor Tuning Scheme for Second-Order LC Filters

This paper presents a scheme to accurately tune the quality factor of second-order LC bandpass filters. The information of the magnitude response at the center and one of the cutoff frequencies is used to tune both the amplitude and the quality factor of the filter using two independent yet interacting loops. Furthermore, the synergic interaction between the loops makes the proposed scheme stable and insensitive to the mismatch between the input amplitudes. A chip prototype was implemented in a 0.35-mum CMOS process and consumes 4.3 mA from a single 1.3-V supply. Measurement results show that at 1.97 GHz the quality factor is tunable from 60 to 220 while the amplitude is tunable between -15 and 0 dBm with worst case quality factor and amplitude tuning accuracies of 10% and 7%, respectivel

A Q-enhanced 3.6 GHz tunable CMOS bandpass filter for wideband wireless applications

With the rapid development of information technology, more and more bandwidth is required to transmit multimedia data. Since local communication networks are moving to wireless domain, it brings up great challenges for making integrated wideband wireless front-ends suitable for these applications. RF filtering is a fundamental need in all wireless front-ends and is one of the most difficult parts to be integrated. This has been a major obstacle to the implementation of low power and low cost integrated wireless terminals. Lots of previous work has been done to make integrated RF filters applicable to these applications. However, some of these filters are not designed with standard CMOS technology. Some of them are not designed in desired frequency bands and others do not have sufficient frequency bandwidth. This research demonstrates the design of a tunable wideband RF filter that operates at 3.6 GHz and can be easily changed to a higher frequency range up to 5 GHz. This filter is superior to the previous designs in the following aspects: a) wider bandwidth, b) easier to tune, c) balancing in noise and linearity, and d) using standard CMOS technology. The design employs the state-of-the-art inductor degenerated LNA, acting as a transconductor to minimize the overall noise figure. A Q-enhancement circuit is employed to compensate the loss from lossy on-chip spiral inductors. Center frequency and bandwidth tuning circuits are also embedded to make the filter suitable for multi band operations. At first, a second order bandpass filter prototype was designed in the standard 0.18 ìm CMOS process. Simulation results showed that at 3.6 GHz center frequency and with a 60-MHz bandwidth, the input third-order intermodulation product (IIP3) and input-referred 1 dB compression point (P1dB) was -22.5 dBm and -30.5 dBm respectively. The image rejection at 500 MHz away from the center frequency was 32 dB (250 MHz intermediate frequency). The Q of the filter was tunable over 3000 and the center frequency tuning range was about 150 MHz. By cascading three stages of second order filters, a sixth order filter was designed to enhance the image rejection ability and to extend the filter bandwidth. The sixth order filter had been fabricated in the standard 0.18 ìm CMOS process using 1.8-V supply. The chip occupies only 0.9 mm 0.9 mm silicon area and has a power consumption of 130-mW. The measured center frequency was tunable from 3.54 GHz to 3.88 GHz, bandwidth was tunable from 35 MHz to 80 MHz. With a 65 MHz bandwidth, the filter had a gain of 13 dB, an IIP3 of -29 dBm and a P1dB of -46 dBm

An RF LC Q-enhanced CMOS iter using integrated inductors with layout optimization

Dissertação apresentada para obtenção do Grau de Mestre em Engenharia Electrotécnica e de Computadores, pela Universidade Nova de Lisboa, Faculdade de Ciências e TecnologiaThe advancement of CMOS technology led to the integration of more complex functions in a single chip. In the particular of wireless transceivers, integrated LC tanks are becoming popular both for VCOs and integrated lters. The design of a 2nd order CMOS 0.13 m Q-enhanced integrated LC lter for a frequency of 2.44 GHz is presented. The intent of this lter is to create a circuit for integrated wireless receiver and minimize the requirement for o -chip passive lter components, reducing the overall component count and size of wireless devices and systems. For RF applications the main challenge is still the design of integrated inductors with the maximum quality factor. For that purpose, tapered, i.e, variable width inductors have been introduced in the literature. In this work, a characterization of variable width integrated inductors is proposed. This inductor model is then integrated into an optimization procedure where inductors with a quality factor improvement are obtained

Design And Analysis Of Cmos Based Rfic Bandpass Filter (BPF) For 1.9GHz Range For CDMA Applications

The rapid development of wireless applications has created a demand for low-cost, compact, low-power hardware solutions. This demand has driven efforts to realize fully integrated, “single-chip” solution systems. While substantial progress had been made in the integration of many RF and baseband processing elements through the development of new technologies and refinements of existing technologies, progress in the area of fully integrated filters has been limited due to the losses (low Q) associated with integrated passive elements in standard IC process. The work in this report focuses on the design and analysis of CMOS based RFIC bandpass filter for center frequency of 1.90Hz. The entire design and analysis of the filter circuit have been carried out by ultilizing Cadence IC Design Tools (version 5.033). This report present a methodology for designing a Q-enhanced bandpass filter with active negative resistance generator circuitry to compensate for the filter losses due to the low quality factor of monolithic spiral inductors. The first phase of this work focus on the design and simulation of an ideal, fully integrated second order Butterworth bandpass filter (with -3dB bandwidth of 200MHz centered at 1.9GHz, corrensponding to the CDMA2000 Standard) ultilizing Cadence IC Design Tools with Silterra 0.18um Design Kit. The ideal bandpass filter which based on the paper work calculation is first constructed by using Silterra SMCMOS ideal component and the simulation results are observed. The ideal circuit is then simulated by using Silterra RF component (which include all parasitic effects) to show the actual filter performance. In the second phase of this work, a FET-based active negative resistance circuit is developed and being added into the bandpass filter circuitry to compensate the filter loss. With features of Cadence IC Design Tools, the filter is analyzed and optimized to obtain the best response. The best filter design achieves ≈ 0dB of passband gain or insertion loss while consuming 8.8mA of current from a ± 1.8V source (31.69mW). The filter provides more than 10dB of rejection at 1.5GHz and 2.5GHz. In the filter passband, the noise figure is 5.25dB and input return loss is -20dB. The filter response only suffered a minor frequency shift for a wide range of operating temperature. The bandpass filter has potential application as RF filters in CMOS integrated transceiver designs