A very high speed lossless compression/decompression chip set

A chip is described that will perform lossless compression and decompression using the Rice Algorithm. The chip set is designed to compress and decompress source data in real time for many applications. The encoder is designed to code at 20 M samples/second at MIL specifications. That corresponds to 280 Mbits/second at maximum quantization or approximately 500 Mbits/second under nominal conditions. The decoder is designed to decode at 10 M samples/second at industrial specifications. A wide range of quantization levels is allowed (4...14 bits) and both nearest neighbor prediction and external prediction are supported. When the pre and post processors are bypassed, the chip set performs high speed entropy coding and decoding. This frees the chip set from being tied to one modeling technique or specific application. Both the encoder and decoder are being fabricated in a 1.0 micron CMOS process that has been tested to survive 1 megarad of total radiation dosage. The CMOS chips are small, only 5 mm on a side, and both are estimated to consume less than 1/4 of a Watt of power while operating at maximum frequency

System architecture study of an orbital GPS user terminal

The generic RF and applications processing requirements for a GPS orbital navigator are considered. A line of demarcation between dedicated analog hardware, and software/processor implementation, maximizing the latter is discussed. A modular approach to R/PA design which permits several varieties of receiver to be constructed from basic components is described. It is a basic conclusion that software signal processing of the output of the baseband correlator is the best choice of transition from analog to digital signal processing. High performance sets requiring multiple channels are developed from a generic design by replicating the RF processing segment, and modifying the applications software to provide enhanced state propagation and estimation

Space station data system analysis/architecture study. Task 2: Options development DR-5. Volume 1: Technology options

The second task in the Space Station Data System (SSDS) Analysis/Architecture Study is the development of an information base that will support the conduct of trade studies and provide sufficient data to make key design/programmatic decisions. This volume identifies the preferred options in the technology category and characterizes these options with respect to performance attributes, constraints, cost, and risk. The technology category includes advanced materials, processes, and techniques that can be used to enhance the implementation of SSDS design structures. The specific areas discussed are mass storage, including space and round on-line storage and off-line storage; man/machine interface; data processing hardware, including flight computers and advanced/fault tolerant computer architectures; and software, including data compression algorithms, on-board high level languages, and software tools. Also discussed are artificial intelligence applications and hard-wire communications

A Portable Piezoelectric Tactile Terminal for Braille Readers

This paper introduces a novel concept on reading assistive technologies for the blind: the TactoBook, a system that is able to translate entire electronic books (eBooks) to Braille code and to reproduce them in portable electronic Braille terminals. The TactoBook consists of a computer-based translator that converts fast and automatically any eBook into Braille. The Braille version of the eBook is then encrypted as a file and stored in a USB memory drive which is later inserted and reproduced in a compact, lightweight, and highly-portable tactile terminal. In particular, this paper presents a piezoelectric ultrasonic actuation approach to design and implement such portable Braille terminal. Actuating mechanism, design concept, first prototype, and performance results are presented and discussed