2,800 research outputs found
Principles of Neuromorphic Photonics
In an age overrun with information, the ability to process reams of data has
become crucial. The demand for data will continue to grow as smart gadgets
multiply and become increasingly integrated into our daily lives.
Next-generation industries in artificial intelligence services and
high-performance computing are so far supported by microelectronic platforms.
These data-intensive enterprises rely on continual improvements in hardware.
Their prospects are running up against a stark reality: conventional
one-size-fits-all solutions offered by digital electronics can no longer
satisfy this need, as Moore's law (exponential hardware scaling),
interconnection density, and the von Neumann architecture reach their limits.
With its superior speed and reconfigurability, analog photonics can provide
some relief to these problems; however, complex applications of analog
photonics have remained largely unexplored due to the absence of a robust
photonic integration industry. Recently, the landscape for
commercially-manufacturable photonic chips has been changing rapidly and now
promises to achieve economies of scale previously enjoyed solely by
microelectronics.
The scientific community has set out to build bridges between the domains of
photonic device physics and neural networks, giving rise to the field of
\emph{neuromorphic photonics}. This article reviews the recent progress in
integrated neuromorphic photonics. We provide an overview of neuromorphic
computing, discuss the associated technology (microelectronic and photonic)
platforms and compare their metric performance. We discuss photonic neural
network approaches and challenges for integrated neuromorphic photonic
processors while providing an in-depth description of photonic neurons and a
candidate interconnection architecture. We conclude with a future outlook of
neuro-inspired photonic processing.Comment: 28 pages, 19 figure
All-Optical Programmable Disaggregated Data Centre Network realized by FPGA-based Switch and Interface Card
This paper reports an FPGA-based switch and interface card (SIC) and its application scenario in an all-optical, programmable disaggregated data center network (DCN). Our novel SIC is designed and implemented to replace traditional optical network interface cards, plugged into the server directly, supporting optical packet switching (OPS)/optical circuit switching (OCS) or time division multiplexing (TDM)/wavelength division multiplexing (WDM) traffic on demand. Placing the SIC in each server/blade, we eliminate electronics from the top of rack (ToR) switch by pushing all the functionality on each blade while enabling direct intrarack blade-to-blade communication to deliver ultralow chip-to-chip latency. We demonstrate the disaggregated DCN architecture scenarios along with all-optical dimension-programmable N × M spectrum selective Switches (SSS) and an architecture-on-demand (AoD) optical backplane. OPS and OCS complement each other as do TDM and WDM, which can support variable traffic flows. A flat disaggregated DCN architecture is realized by connecting the optical ToR switches directly to either an optical top of cluster switch or the intracluster AoD optical backplane, while clusters are further interconnected to an intercluster AoD for scaling out
Experimental Evaluation and Comparison of Time-Multiplexed Multi-FPGA Routing Architectures
Emulating large complex designs require multi-FPGA systems (MFS). However, inter-FPGA communication is confronted by the challenge of lack of interconnect capacity due to limited number of FPGA input/output (I/O) pins. Serializing parallel signals onto a single trace effectively addresses the limited I/O pin obstacle. Besides the multiplexing scheme and multiplexing ratio (number of inter-FPGA signals per trace), the choice of the MFS routing architecture also affect the critical path latency. The routing architecture of an MFS is the interconnection pattern of FPGAs, fixed wires and/or programmable interconnect chips. Performance of existing MFS routing architectures is also limited by off-chip interface selection. In this dissertation we proposed novel 2D and 3D latency-optimized time-multiplexed MFS routing architectures. We used rigorous experimental approach and real sequential benchmark circuits to evaluate and compare the proposed and existing MFS routing architectures. This research provides a new insight into the encouraging effects of using off-chip optical interface and three dimensional MFS routing architectures. The vertical stacking results in shorter off-chip links improving the overall system frequency with the additional advantage of smaller footprint area. The proposed 3D architectures employed serialized interconnect between intra-plane and inter-plane FPGAs to address the pin limitation problem. Additionally, all off-chip links are replaced by optical fibers that exhibited latency improvement and resulted in faster MFS. Results indicated that exploiting third dimension provided latency and area improvements as compared to 2D MFS. We also proposed latency-optimized planar 2D MFS architectures in which electrical interconnections are replaced by optical interface in same spatial distribution. Performance evaluation and comparison showed that the proposed architectures have reduced critical path delay and system frequency improvement as compared to conventional MFS. We also experimentally evaluated and compared the system performance of three inter-FPGA communication schemes i.e. Logic Multiplexing, SERDES and MGT in conjunction with two routing architectures i.e. Completely Connected Graph (CCG) and TORUS. Experimental results showed that SERDES attained maximum frequency than the other two schemes. However, for very high multiplexing ratios, the performance of SERDES & MGT became comparable
Benchmarking and viability assessment of optical packet switching for metro networks
Optical packet switching (OPS) has been proposed as a strong candidate for future metro networks. This paper assesses the viability of an OPS-based ring architecture as proposed within the research project DAVID (Data And Voice Integration on DWDM), funded by the European Commission through the Information Society Technologies (IST) framework. Its feasibility is discussed from a physical-layer point of view, and its limitations in size are explored. Through dimensioning studies, we show that the proposed OPS architecture is competitive with respect to alternative metropolitan area network (MAN) approaches, including synchronous digital hierarchy, resilient packet rings (RPR), and star-based Ethernet. Finally, the proposed OPS architectures are discussed from a logical performance point of view, and a high-quality scheduling algorithm to control the packet-switching operations in the rings is explained
Application of novel technologies for the development of next generation MR compatible PET inserts
Multimodal imaging integrating Positron Emission Tomography and Magnetic
Resonance Imaging (PET/MRI) has professed advantages as compared to other available
combinations, allowing both functional and structural information to be acquired with
very high precision and repeatability. However, it has yet to be adopted as the standard
for experimental and clinical applications, due to a variety of reasons mainly related to
system cost and flexibility. A hopeful existing approach of silicon photodetector-based MR
compatible PET inserts comprised by very thin PET devices that can be inserted in the
MRI bore, has been pioneered, without disrupting the market as expected. Technological
solutions that exist and can make this type of inserts lighter, cost-effective and more
adaptable to the application need to be researched further.
In this context, we expand the study of sub-surface laser engraving (SSLE) for
scintillators used for PET. Through acquiring, measuring and calibrating the use of a SSLE
setting we study the effect of different engraving configurations on detection
characteristics of the scintillation light by the photosensors. We demonstrate that apart
from cost-effectiveness and ease of application, SSLE treated scintillators have similar
spatial resolution and superior sensitivity and packing fraction as compared to standard
pixelated arrays, allowing for shorter crystals to be used. Flexibility of design is
benchmarked and adoption of honeycomb architecture due to geometrical advantages is
proposed. Furthermore, a variety of depth-of-interaction (DoI) designs are engraved and
studied, greatly enhancing applicability in small field-of-view tomographs, such as the
intended inserts. To adapt to this need, a novel approach for multi-layer DoI
characterization has been developed and is demonstrated.
Apart from crystal treatment, considerations on signal transmission and processing are
addressed. A double time-over-threshold (ToT) method is proposed, using the statistics of
noise in order to enhance precision. This method is tested and linearity results
demonstrate applicability for multiplexed readout designs. A study on analog optical
wireless communication (aOWC) techniques is also performed and proof of concept
results presented. Finally, a ToT readout firmware architecture, intended for low-cost
FPGAs, has been developed and is described.
By addressing the potential development, applicability and merits of a range of
transdisciplinary solutions, we demonstrate that with these techniques it is possible to
construct lighter, smaller, lower consumption, cost-effective MRI compatible PET inserts.
Those designs can make PET/MRI multimodality the dominant clinical and experimental
imaging approach, enhancing researcher and physician insight to the mysteries of life.La combinación multimodal de Tomografía por Emisión de Positrones con la Imagen de
Resonancia Magnética (PET/MRI, de sus siglas en inglés) tiene clara ventajas en
comparación con otras técnicas multimodales actualmente disponibles, dada su capacidad
para registrar información funcional e información estructural con mucha precisión y
repetibilidad. Sin embargo, esta técnica no acaba de penetrar en la práctica clínica debido
en gran parte a alto coste. Las investigaciones que persiguen mejorar el desarrollo de
insertos de PET basados en fotodetectores de silicio y compatibles con MRI, aunque han
sido intensas y han generado soluciones ingeniosas, todavía no han conseguido encontrar
las soluciones que necesita la industria. Sin embargo, existen opciones todavía sin explorar
que podrían ayudar a evolucionar este tipo de insertos consiguiendo dispositivos más
ligeros, baratos y con mejores prestaciones.
Esta tesis profundiza en el estudio de grabación sub-superficie con láser (SSLE) para el
diseño de los cristales centelladores usados en los sistemas PET. Para ello hemos
caracterizado, medido y calibrado un procedimiento SSLE, y a continuación hemos
estudiado el efecto que tienen sobre las especificaciones del detector las diferentes
configuraciones del grabado. Demostramos que además de la rentabilidad y facilidad de
uso de esta técnica, los centelladores SSLE tienen resolución espacial equivalente y
sensibilidad y fracción de empaquetamiento superiores a las matrices de centelleo
convencionales, lo que posibilita utilizar cristales más cortos para conseguir la misma
sensibilidad. Estos diseños también permiten medir la profundidad de la interacción (DoI),
lo que facilita el uso de estos diseños en tomógrafos de radio pequeño, como pueden ser
los sistemas preclínicos, los dedicados (cabeza o mama) o los insertos para MRI.
Además de trabajar en el tratamiento de cristal de centelleo, hemos considerado nuevas
aproximaciones al procesamiento y transmisión de la señal. Proponemos un método
innovador de doble medida de tiempo sobre el umbral (ToT) que integra una evaluación
de la estadística del ruido con el propósito de mejorar la precisión. El método se ha
validado y los resultados demuestran su viabilidad de uso incluso en conjuntos de señales
multiplexadas. Un estudio de las técnicas de comunicación óptica analógica e inalámbrica
(aOWC) ha permitido el desarrollo de una nueva propuesta para comunicar las señales del
detector PET insertado en el gantry a un el procesador de señal externo, técnica que se ha
validado en un demostrador. Finalmente, se ha propuesto y demostrado una nueva
arquitectura de análisis de señal ToT implementada en firmware en FPGAs de bajo coste.
La concepción y desarrollo de estas ideas, así como la evaluación de los méritos de las
diferentes soluciones propuestas, demuestran que con estas técnicas es posible construir
insertos de PET compatibles con sistemas MRI, que serán más ligeros y compactos, con un
reducido consumo y menor coste. De esta forma se contribuye a que la técnica multimodal
PET/MRI pueda penetrar en la clínica, mejorando la comprensión que médicos e
investigadores puedan alcanzar en su estudio de los misterios de la vida.Programa Oficial de Doctorado en Ingeniería Eléctrica, Electrónica y AutomáticaPresidente: Andrés Santos Lleó.- Secretario: Luis Hernández Corporales.- Vocal: Giancarlo Sportell
On-Chip Optical Interconnection Networks for Multi/Manycore Architectures
The rapid development of multi/manycore technologies offers the opportunity for highly parallel architectures implemented on a single chip. While the first, low-parallelism multicore products have been based on simple interconnection structures (single bus, very simple crossbar), the emerging highly parallel architectures will require complex, limited-degree interconnection networks. This thesis studies this trend according to the general theory of interconnection structures for parallel machines, and investigates some solutions in terms of performance, cost, fault-tolerance, and run-time support to shared-memory and/or message passing programming mechanisms
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