Very low thermal drift precision virtual voltage reference

A digital-based, process-supply-and-temperature independent voltage reference suitable to nanoscale CMOS technologies, which exploits the recently proposed ‘virtual reference’ concept to achieve a very low thermal drift, is presented. Its performance is assessed on the basis of simulations and experiments carried out on a microcontroller-based, proof-of-concept prototype and is compared with state-of-the-art integrated analogue and digital voltage references. A simulated (measured) thermal drift as low as 1 ppm/°C (5 ppm/°C) in the temperature range −40/+140°C (−10/+100°C) is reported

Estudio del diseño de un circuito de voltaje de referencia para aplicaciones de bajo voltaje y bajo consumo de energía

Este trabajo de investigación describe el funcionamiento de los circuitos que permiten la generación de un voltaje de referencia estable ante variaciones en la temperatura y el voltaje de alimentación. Las topologías clásicas de circuitos de voltaje de referencia limitan el voltaje que entregan a valores cercanos a 1.2 V, impidiendo que aplicaciones de menor voltaje puedan hacer uso de dichos circuitos. El principal inconveniente yace en que las topologías clásicas de estos circuitos limitan el voltaje que entregan a valores cercanos a 1.2 V. Actualmente muchos circuitos integrados se diseñan para operar con voltajes menores a 1.2 V, de modo que es necesario plantear las consideraciones que permitan el diseño de un circuito de voltaje de referencia de bajo voltaje. El propósito de este trabajo de investigación es exponer los fundamentos para el diseño de un circuito de voltaje de referencia. Se desarrolla la teoría que permite la obtención de un voltaje independiente de la temperatura. Posteriormente se analizan dos topologías: una convencional y otra de bajo voltaje. Esta última sirve de referencia para el diseño de voltaje de referencia de bajo voltaje. En la parte final de esta investigación se enuncian conclusiones sobre el marco teórico revisado. También se mencionan recomendaciones para el diseño de un circuito de bajo voltaje.Trabajo de investigació

Design of a Programmable Passive SoC for Biomedical Applications Using RFID ISO 15693/NFC5 Interface

Low power, low cost inductively powered passive biotelemetry system involving fully customized RFID/NFC interface base SoC has gained popularity in the last decades. However, most of the SoCs developed are application specific and lacks either on-chip computational or sensor readout capability. In this paper, we present design details of a programmable passive SoC in compliance with ISO 15693/NFC5 standard for biomedical applications. The integrated system consists of a 32-bit microcontroller, a sensor readout circuit, a 12-bit SAR type ADC, 16 kB RAM, 16 kB ROM and other digital peripherals. The design is implemented in a 0.18 μ m CMOS technology and used a die area of 1.52 mm × 3.24 mm. The simulated maximum power consumption of the analog block is 592 μ W. The number of external components required by the SoC is limited to an external memory device, sensors, antenna and some passive components. The external memory device contains the application specific firmware. Based on the application, the firmware can be modified accordingly. The SoC design is suitable for medical implants to measure physiological parameters like temperature, pressure or ECG. As an application example, the authors have proposed a bioimplant to measure arterial blood pressure for patients suffering from Peripheral Artery Disease (PAD)

An Ultra-Low-Power RFID/NFC Frontend IC Using 0.18 μm CMOS Technology for Passive Tag Applications

Battery-less passive sensor tags based on RFID or NFC technology have achieved much popularity in recent times. Passive tags are widely used for various applications like inventory control or in biotelemetry. In this paper, we present a new RFID/NFC frontend IC (integrated circuit) for 13.56 MHz passive tag applications. The design of the frontend IC is compatible with the standard ISO 15693/NFC 5. The paper discusses the analog design part in details with a brief overview of the digital interface and some of the critical measured parameters. A novel approach is adopted for the demodulator design, to demodulate the 10% ASK (amplitude shift keying) signal. The demodulator circuit consists of a comparator designed with a preset offset voltage. The comparator circuit design is discussed in detail. The power consumption of the bandgap reference circuit is used as the load for the envelope detection of the ASK modulated signal. The sub-threshold operation and low-supply-voltage are used extensively in the analog design—to keep the power consumption low. The IC was fabricated using 0.18 μ m CMOS technology in a die area of 1.5 mm × 1.5 mm and an effective area of 0.7 m m 2 . The minimum supply voltage desired is 1.2 V, for which the total power consumption is 107 μ W. The analog part of the design consumes only 36 μ W, which is low in comparison to other contemporary passive tags ICs. Eventually, a passive tag is developed using the frontend IC, a microcontroller, a temperature and a pressure sensor. A smart NFC device is used to readout the sensor data from the tag employing an Android-based application software. The measurement results demonstrate the full passive operational capability. The IC is suitable for low-power and low-cost industrial or biomedical battery-less sensor applications. A figure-of-merit (FOM) is proposed in this paper which is taken as a reference for comparison with other related state-of-the-art researches

Low temperature coefficient bandgap voltage reference generator

The maximum achievable performance of almost all mixed-signal and radio frequency systems is dependent on the accuracy of voltage references. The bandgap voltage of silicon at zero Kelvin, VGO is a physical constant with unit Volts. It is independent of process, supply voltage and temperature variations. This work proposes a strategy for extracting VGO and expressing it at the output of a voltage reference circuit. The concept is implemented in UMC 65nm process and the simulation results indicate that the circuit design can achieve very low temperature coefficients (\u3c1ppm/°C). The proposed concept is validated using measurements and the associated constraints are carefully investigated. The measured output voltage reference of the two tested units record a temperature coefficient of 3.4ppm/°C and 4.57ppm/°C across the industrial temperature range (-40°C to 85°C)

Ultra-low power mixed-signal frontend for wearable EEGs

Electronics circuits are ubiquitous in daily life, aided by advancements in the chip design industry, leading to miniaturised solutions for typical day to day problems. One of the critical healthcare areas helped by this advancement in technology is electroencephalography (EEG). EEG is a non-invasive method of tracking a person's brain waves, and a crucial tool in several healthcare contexts, including epilepsy and sleep disorders. Current ambulatory EEG systems still suffer from limitations that affect their usability. Furthermore, many patients admitted to emergency departments (ED) for a neurological disorder like altered mental status or seizures, would remain undiagnosed hours to days after admission, which leads to an elevated rate of death compared to other conditions. Conducting a thorough EEG monitoring in early-stage could prevent further damage to the brain and avoid high mortality. But lack of portability and ease of access results in a long wait time for the prescribed patients. All real signals are analogue in nature, including brainwaves sensed by EEG systems. For converting the EEG signal into digital for further processing, a truly wearable EEG has to have an analogue mixed-signal front-end (AFE). This research aims to define the specifications for building a custom AFE for the EEG recording and use that to review the suitability of the architectures available in the literature. Another critical task is to provide new architectures that can meet the developed specifications for EEG monitoring and can be used in epilepsy diagnosis, sleep monitoring, drowsiness detection and depression study. The thesis starts with a preview on EEG technology and available methods of brainwaves recording. It further expands to design requirements for the AFE, with a discussion about critical issues that need resolving. Three new continuous-time capacitive feedback chopped amplifier designs are proposed. A novel calibration loop for setting the accurate value for a pseudo-resistor, which is a crucial block in the proposed topology, is also discussed. This pseudoresistor calibration loop achieved the resistor variation of under 8.25%. The thesis also presents a new design of a curvature corrected bandgap, as well as a novel DDA based fourth-order Sallen-Key filter. A modified sensor frontend architecture is then proposed, along with a detailed analysis of its implementation. Measurement results of the AFE are finally presented. The AFE consumed a total power of 3.2A (including ADC, amplifier, filter, and current generation circuitry) with the overall integrated input-referred noise of 0.87V-rms in the frequency band of 0.5-50Hz. Measurement results confirmed that only the proposed AFE achieved all defined specifications for the wearable EEG system with the smallest power consumption than state-of-art architectures that meet few but not all specifications. The AFE also achieved a CMRR of 131.62dB, which is higher than any studied architectures.Open Acces

Design and verification approaches for reliability and functional safety of analog integrated circuits

New breakthroughs in semiconductor design have enabled a rapid integration of semiconductor chips into systems that affect all aspects of the society. Examples of emerging systems include spacecraft, Internet of Things (IoT), intelligent automotive, and bio-implantable devices. Many of these systems are mission-critical or safety-critical, meaning that failure or malfunction may lead to severe economical losses, environmental damages or risks to human lives. In addition to performances improvement, the reliability and functional safety of the underlying integrated circuit (IC) have attracted more and more attention and have posed grand challenges for semiconductor industries. This dissertation introduces an approach for high performance voltage reference design and investigates two subjects that improve the reliability and functional safety of analog circuits. The first part of this dissertation studies design strategies of a low temperature-coefficient voltage reference generator, which is a fundamental building block and determines the maximum achievable performance of almost all analog/mixed-signal systems. The proposed method is targeted at extracting a physical quantity of the silicon bandgap, and has the potential of designing a voltage reference that has qualitatively better temperature dependence. An implementation of the proposed approach in GlobalFoundries 130nm process shows that the design can achieve temperature coefficients as low as 0.7ppm/°C over a temperature range of -40°C to 125°C over all process corners. The second part of this dissertation focuses on multi-states verification of analog circuits. The multiple DC equilibrium points or multi-states problem traces back to IC design. It is a well-known problem in many basic self-stabilized analog circuits because of the existence of positive feedback loops (PFLs). This work proposes systematic and automatic approaches for locating all PFLs to identify circuits vulnerable to undesired equilibrium states and methods for automatically identifying break-points to break all PFLs in the vulnerable circuits. The proposed methods make it possible to efficiently identify a circuit’s vulnerability to undesired operating points by considering circuit topology only, without the need for finding all possible solutions to a set of simultaneous nonlinear equations which is an open problem with no solution. Moreover, the automatic break-points identification enables easy use of homotopy analysis to guarantee absence of undesired states. The third part of this dissertation focuses on fault coverage simulation of analog circuits. This work describe two methods, one is to reduce the fault coverage estimation time and the other is to improve the fault coverage for analog circuits. The first method incorporates graph theory and sensitivity analysis and leads to dramatic reduction in fault coverage simulation time by 10’s of times for a moderately sized analog circuit. The second method discusses a systematic test-points selection technique to improve the analog fault coverage with simple DC tests and a concurrent sampling technique for monitoring these points. This work could be applied to manufacturing testing or for real-time fault detection