A Non-Linear Feedback Current Driver With Automatic Phase Compensation for Bioimpedance Applications

In a conventional sinewave current driver for electrical impedance spectroscopy, as the frequency is increased the input/output phase delay of the current driver increases due to limited bandwidth. The required maximum phase delays of < 4o mean that operation is limited to about 1/12 of the driver bandwidth. A new phase compensation scheme is presented to reduce the phase delay at higher frequencies and can extend the useful operating frequency range of a current driver. The system is capable of reducing the phase error due to the current driver by an appreciable level so that it can operate much nearer the pole frequency of the driver. An integrated circuit was fabricated in a 0.35 5m CMOS process technology which provides a phase error reduction from 22o to 3o at 3 MHz. Its core occupies a silicon area of 1.2 mm2. It operates from a ±2.5 V power supply and can deliver output currents up to 1.8 mAp-p at 3 MHz

High-power CMOS current driver with accurate transconductance for electrical impedance tomography

Current drivers are fundamental circuits in bioimpedance measurements including electrical impedance tomography (EIT). In the case of EIT, the current driver is required to have a large output impedance to guarantee high current accuracy over a wide range of load impedance values. This paper presents an integrated current driver which meets these requirements and is capable of delivering large sinusoidal currents to the load. The current driver employs a differential architecture and negative feedback, the latter allowing the output current to be accurately set by the ratio of the input voltage to a resistor value. The circuit was fabricated in a 0.6-μ m high-voltage CMOS process technology and its core occupies a silicon area of 0.64 mm2. It operates from a ± 9 V power supply and can deliver output currents up to 5 mA p-p. The accuracy of the maximum output current is within 0.41% up to 500 kHz, reducing to 0.47% at 1 MHz with a total harmonic distortion of 0.69%. The output impedance is 665 kΩ at 100 kHz and 372 k Ω at 500 kHz

A low-power recursive I/Q signal generator and current driver for bioimpedance applications

This brief presents a power-efficient quadrature signal generator and current driver application-specific integrated circuit (ASIC) for bioimpedance measurements in an electrical impedance tomography system for monitoring lung function. The signal generator is realized by a digital recursive signal oscillator with the ability of generating quadrature signals over a wide frequency range. The generated in-phase signal is applied to a current driver. It uses a balanced current-mode feedback architecture that monitors the output current through a feedback loop to minimize common-mode voltage build-up at the injection site. The quadrature signals can be used for I/Q demodulation of the measured bioimpedance. The ASIC was designed in TSMC 65 nm technology occupying an area of 0.21 mm2. The current driver can generate up to 0.7 mA current up to 200 kHz and consumes 2.7 mW power using ±0.8 V supplies

An 89.3% Current Efficiency, Sub 0.1% THD Current Driver for Electrical Impedance Tomography

Accurate electrical impedance tomography (EIT) measurements require a current driver with low total harmonic distortion (THD) and high output impedance. Conventional EIT current drivers attain good performance for these parameters but at the expense of low current efficiency. This Brief presents a differential current driver based on a current feedback structure with isolated common-mode feedback, achieving very low THD, high output impedance and high current efficiency. In addition, it uses current DACs to remove any dc offsets at the output nodes. The current driver was fabricated in a 65-nm CMOS technology with 3.3 V supply. Measured results demonstrate a THD of 0.05% and 0.1% at 80 kHz, for 1 mAp-p and 1.375 mAp-p output current, respectively. The total current consumption is 1.54 mA, resulting in a maximum current efficiency of 89.3%. The measured output impedance is 1.023 MΩ at 500 kHz and 568 kΩ at 1 MHz

An 89.3% current efficiency, sub 0.1% THD current driver for electrical impedance tomography

Accurate electrical impedance tomography (EIT) measurements require a current driver with low total harmonic distortion (THD) and high output impedance. Conventional EIT current drivers attain good performance for these parameters but at the expense of low current efficiency. This Brief presents a differential current driver based on a current feedback structure with isolated common-mode feedback, achieving very low THD, high output impedance and high current efficiency. In addition, it uses current DACs to remove any dc offsets at the output nodes. The current driver was fabricated in a 65-nm CMOS technology with 3.3 V supply. Measured results demonstrate a THD of 0.05% and 0.1% at 80 kHz, for 1mAp−p and 1.375mAp−p output current, respectively. The total current consumption is 1.54 mA, resulting in a maximum current efficiency of 89.3%. The measured output impedance is 1.023 MΩ at 500 kHz and 568 kΩ at 1 MHz

Electrical Impedance Tomography for Biomedical Applications: Circuits and Systems Review

There has been considerable interest in electrical impedance tomography (EIT) to provide low-cost, radiation-free, real-time and wearable means for physiological status monitoring. To be competitive with other well-established imaging modalities, it is important to understand the requirements of the specific application and determine a suitable system design. This paper presents an overview of EIT circuits and systems including architectures, current drivers, analog front-end and demodulation circuits, with emphasis on integrated circuit implementations. Commonly used circuit topologies are detailed, and tradeoffs are discussed to aid in choosing an appropriate design based on the application and system priorities. The paper also describes a number of integrated EIT systems for biomedical applications, as well as discussing current challenges and possible future directions

Wideband Fully-Programmable Dual-Mode CMOS Analogue Front-End for Electrical Impedance Spectroscopy

This paper presents a multi-channel dual-mode CMOS analogue front-end (AFE) for electrochemical and bioimpedance analysis. Current-mode and voltage-mode readouts, integrated on the same chip, can provide an adaptable platform to correlate single-cell biosensor studies with large-scale tissue or organ analysis for real-time cancer detection, imaging and characterization. The chip, implemented in a 180-nm CMOS technology, combines two current-readout (CR) channels and four voltage-readout (VR) channels suitable for both bipolar and tetrapolar electrical impedance spectroscopy (EIS) analysis. Each VR channel occupies an area of 0.48 mm 2 , is capable of an operational bandwidth of 8 MHz and a linear gain in the range between -6 dB and 42 dB. The gain of the CR channel can be set to 10 kΩ, 50 kΩ or 100 kΩ and is capable of 80-dB dynamic range, with a very linear response for input currents between 10 nA and 100 μ A. Each CR channel occupies an area of 0.21 mm 2 . The chip consumes between 530 μ A and 690 μ A per channel and operates from a 1.8-V supply. The chip was used to measure the impedance of capacitive interdigitated electrodes in saline solution. Measurements show close matching with results obtained using a commercial impedance analyser. The chip will be part of a fully flexible and configurable fully-integrated dual-mode EIS system for impedance sensors and bioimpedance analysis

A Low Power, Low THD Current Driver with Discrete Common-Mode Feedback for EIT Applications

A low THD sinusoidal current driver for electrical impedance tomography (EIT) applications is proposed and analyzed in this paper. A discrete common-mode feedback method is proposed to increase the accuracy of the output current amplitude and output impedance. The current driver is designed in 65 nm technology under 3.3 V supply with a chip area of 0.0843 mm2. The maximum output current amplitude is 1.2 mA. In simulations the current driver achieves an average THD of 0.098% at 1 mA output current amplitude and 500 kHz output current frequency. The simulated output impedance is higher than 4 MΩ at a load impedance lower than 3.5 kΩ. The current consumption of the circuit is 1.47 mA and provides a current efficiency of 81.6%

A high frame rate wearable EIT system using active electrode ASICs for lung respiration and heart rate monitoring

A high specification, wearable, electrical impedance tomography (EIT) system with 32 active electrodes is presented. Each electrode has an application specific integrated circuit (ASIC) mounted on a flexible printed circuit board, which is then wrapped inside a disposable fabric cover containing silver-coated electrodes to form the wearable belt. It is connected to a central hub that operates all the 32 ASICs. Each ASIC comprises a high- performance current driver capable of up to 6 mAp−p output, a voltage buffer for EIT and heart rate signal recording as well as contact impedance monitoring, and a sensor buffer that provides multi-parameter sensing. The ASIC was designed in a CMOS 0.35-μm high-voltage process technology. It operates from ±9-V power supplies and occupies a total die area of 3.9 mm2. The EIT system has a bandwidth of 500 kHz and employs two parallel data acquisition channels to achieve a frame rate of 107 frames/s, the fastest wearable EIT system reported to date. Measured results show that the system has a measurement accuracy of 98.88% and a minimum EIT detectability of 0.86 Q/frame. Its successful operation in capturing EIT lung respiration and heart rate biosignals from a volunteer is demonstrated

A high frame rate wearable EIT system using active electrode ASICs for lung respiration and heart rate monitoring

A high specification, wearable, electrical impedance tomography (EIT) system with 32 active electrodes is presented. Each electrode has an application specific integrated circuit (ASIC) mounted on a flexible printed circuit board, which is then wrapped inside a disposable fabric cover containing silver-coated electrodes to form the wearable belt. It is connected to a central hub that operates all the 32 ASICs. Each ASIC comprises a high- performance current driver capable of up to 6 mAp−p output, a voltage buffer for EIT and heart rate signal recording as well as contact impedance monitoring, and a sensor buffer that provides multi-parameter sensing. The ASIC was designed in a CMOS 0.35-μm high-voltage process technology. It operates from ±9-V power supplies and occupies a total die area of 3.9 mm2. The EIT system has a bandwidth of 500 kHz and employs two parallel data acquisition channels to achieve a frame rate of 107 frames/s, the fastest wearable EIT system reported to date. Measured results show that the system has a measurement accuracy of 98.88% and a minimum EIT detectability of 0.86 Q/frame. Its successful operation in capturing EIT lung respiration and heart rate biosignals from a volunteer is demonstrated