Linear Current-Mode Active Pixel Sensor

A current mode CMOS active pixel sensor (APS) providing linear light-to-current conversion with inherently low fixed pattern noise (FPN) is presented. The pixel features adjustable-gain current output using a pMOS readout transistor in the linear region of operation. This paper discusses the pixel’s design and operation, and presents an analysis of the pixel’s temporal noise and FPN. Results for zero and first-order pixel mismatch are presented. The pixel was implemented in a both a 3.3 V 0.35 µm and a 1.8 V 0.18 µm CMOS process. The 0.35 µm process pixel had an uncorrected FPN of 1.4%/0.7% with/without column readout mismatch. The 0.18 µm process pixel had 0.4% FPN after delta-reset sampling (DRS). The pixel size in both processes was 10 X 10 µm2, with fill factors of 26% and 66%, respectively

Polarization Imaging Sensors in Advanced Feature CMOS Technologies

The scaling of CMOS technology, as predicted by Moore\u27s law, has allowed for realization of high resolution imaging sensors and for the emergence of multi-mega-pixel imagers. Designing imaging sensors in advanced feature technologies poses many challenges especially since transistor models do not accurately portray their performance in these technologies. Furthermore, transistors fabricated in advanced feature technologies operate in a non-conventional mode known as velocity saturation. Traditionally, analog designers have been discouraged from designing circuits in this mode of operation due to the low gain properties in single transistor amplifiers. Nevertheless, velocity saturation will become even more prominent mode of operation as transistors continue to shrink and warrants careful design of circuits that can exploit this mode of operation. In this research endeavor, I have utilized velocity saturation mode of operation in order to realize low noise imaging sensors. These imaging sensors incorporate low noise analog circuits at the focal plane in order to improve the signal to noise ratio and are fabricated in 0.18 micron technology. Furthermore, I have explored nanofabrication techniques for realizing metallic nanowires acting as polarization filters. These nanoscopic metallic wires are deposited on the surface of the CMOS imaging sensor in order to add polarization sensitivity to the CMOS imaging sensor. This hybrid sensor will serve as a test bed for exploring the next generation of low noise and highly sensitive polarization imaging sensors

A 64k pixel CMOS-DEPFET module for the soft X-rays DSSC imager operating at MHz-frame rates

: The 64k pixel DEPFET module is the key sensitive component of the DEPFET Sensor with Signal Compression (DSSC), a large area 2D hybrid detector for capturing and measuring soft X-rays at the European XFEL. The final 1-megapixel camera has to detect photons with energies between [Formula: see text] and [Formula: see text], and must provide a peak frame rate of [Formula: see text] to cope with the unique bunch structure of the European XFEL. This work summarizes the functionalities and properties of the first modules assembled with full-format CMOS-DEPFET arrays, featuring [Formula: see text] hexagonally-shaped pixels with a side length of 136 μm. The pixel sensors utilize the DEPFET technology to realize an extremely low input capacitance for excellent energy resolution and, at the same time, an intrinsic capability of signal compression without any gain switching. Each pixel of the readout ASIC includes a DEPFET-bias current cancellation circuitry, a trapezoidal-shaping filter, a 9-bit ADC and a 800-word long digital memory. The trimming, calibration and final characterization were performed in a laboratory test-bench at DESY. All detector features are assessed at [Formula: see text]. An outstanding equivalent noise charge of [Formula: see text]e-rms is achieved at 1.1-MHz frame rate and gain of 26.8 Analog-to-Digital Unit per keV ([Formula: see text]). At [Formula: see text] and [Formula: see text], a noise of [Formula: see text] e-rms and a dynamic range of [Formula: see text] are obtained. The highest dynamic range of [Formula: see text] is reached at [Formula: see text] and [Formula: see text]. These values can fulfill the specification of the DSSC project

Active Pixel Sensor Architectures for High Resolution Large Area Digital Imaging

This work extends the technology of amorphous silicon (a-Si) thin film transistors (TFTs) from traditional switching applications to on-pixel signal amplification for large area digital imaging and in particular, is aimed towards enabling emerging low noise, high resolution and high frame rate medical diagnostic imaging modalities such as digital tomosynthesis. A two transistor (2T) pixel amplifier circuit based on a novel charge-gate thin film transistor (TFT) device architecture is introduced to shrink the TFT based pixel readout circuit size and complexity and thus, improve the imaging array resolution and reliability of the TFT fabrication process. The high resolution pixel amplifier results in improved electrical performance such as on-pixel amplification gain, input referred noise and faster readouts. In this research, a charge-gated TFT that operates as both a switched amplifier and driver is used to replace two transistors (the addressing switch and the amplifier transistor) of previously reported three transistor (3T) APS pixel circuits.. In addition to enabling smaller pixels, the proposed 2T pixel amplifier results in better signal-to-noise (SNR) by removing the large flicker noise source associated with the switched TFT and increased pixel transconductance gain since the large ON-state resistance of the switched TFT is removed from the source of the amplifier TFT. Alternate configurations of 2T APS architectures based on source or drain switched TFTs are also investigated, compared, and contrasted to the gate switched architecture using charge-gated TFT. A new driving scheme based on multiple row resetting is introduced which combined with the on-pixel gain of the APS, offers considerable improvements in imaging frame rates beyond those feasible for PPS based pixels. The novel developed 2T APS architectures is implemented in single pixel test structures and in 88 pixel test arrays with a pixel pitch of 100 µm. The devices were fabricated using an in-house developed top-gate TFT fabrication process. Measured characteristics of the test devices confirm the performance expectations of the 2T architecture design. Based on parameters extracted from fabricated TFTs, the input referred noise is calculated, and the instability in pixel transconductance gain over prolonged operation tine is projected for different imaging frame rates. 2T APS test arrays were packaged and integrated with an amorphous selenium (a-Se) direct x-ray detector, and the x-ray response of the a-Se detector integrated with the novel readout circuit was evaluated. The special features of the APS such as non-destructive readout and voltage programmable on-pixel gain control are verified. The research presented in this thesis extends amorphous silicon pixel amplifier technology into the area of high density pixel arrays such as large area medical X-ray imagers for digital mammography tomosynthesis. It underscores novel device and circuit design as an effective method of overcoming the inherent shortcomings of the a-Si material . Although the developed device and circuit ideas were implemented and tested using a-Si TFTs, the scope of the device and circuit designs is not limited to amorphous silicon technology and has the potential to be applied to more mainstream technologies, for example, in CMOS active pixel sensor (APS) based digital cameras

Interfacing of neuromorphic vision, auditory and olfactory sensors with digital neuromorphic circuits

The conventional Von Neumann architecture imposes strict constraints on the development of intelligent adaptive systems. The requirements of substantial computing power to process and analyse complex data make such an approach impractical to be used in implementing smart systems. Neuromorphic engineering has produced promising results in applications such as electronic sensing, networking architectures and complex data processing. This interdisciplinary field takes inspiration from neurobiological architecture and emulates these characteristics using analogue Very Large Scale Integration (VLSI). The unconventional approach of exploiting the non-linear current characteristics of transistors has aided in the development of low-power adaptive systems that can be implemented in intelligent systems. The neuromorphic approach is widely applied in electronic sensing, particularly in vision, auditory, tactile and olfactory sensors. While conventional sensors generate a huge amount of redundant output data, neuromorphic sensors implement the biological concept of spike-based output to generate sparse output data that corresponds to a certain sensing event. The operation principle applied in these sensors supports reduced power consumption with operating efficiency comparable to conventional sensors. Although neuromorphic sensors such as Dynamic Vision Sensor (DVS), Dynamic and Active pixel Vision Sensor (DAVIS) and AEREAR2 are steadily expanding their scope of application in real-world systems, the lack of spike-based data processing algorithms and complex interfacing methods restricts its applications in low-cost standalone autonomous systems. This research addresses the issue of interfacing between neuromorphic sensors and digital neuromorphic circuits. Current interfacing methods of these sensors are dependent on computers for output data processing. This approach restricts the portability of these sensors, limits their application in a standalone system and increases the overall cost of such systems. The proposed methodology simplifies the interfacing of these sensors with digital neuromorphic processors by utilizing AER communication protocols and neuromorphic hardware developed under the Convolution AER Vision Architecture for Real-time (CAVIAR) project. The proposed interface is simulated using a JAVA model that emulates a typical spikebased output of a neuromorphic sensor, in this case an olfactory sensor, and functions that process this data based on supervised learning. The successful implementation of this simulation suggests that the methodology is a practical solution and can be implemented in hardware. The JAVA simulation is compared to a similar model developed in Nengo, a standard large-scale neural simulation tool. The successful completion of this research contributes towards expanding the scope of application of neuromorphic sensors in standalone intelligent systems. The easy interfacing method proposed in this thesis promotes the portability of these sensors by eliminating the dependency on computers for output data processing. The inclusion of neuromorphic Field Programmable Gate Array (FPGA) board allows reconfiguration and deployment of learning algorithms to implement adaptable systems. These low-power systems can be widely applied in biosecurity and environmental monitoring. With this thesis, we suggest directions for future research in neuromorphic standalone systems based on neuromorphic olfaction

INTEGRATED SINGLE-PHOTON SENSING AND PROCESSING PLATFORM IN STANDARD CMOS

Practical implementation of large SPAD-based sensor arrays in the standard CMOS process has been fraught with challenges due to the many performance trade-offs existing at both the device and the system level [1]. At the device level the performance challenge stems from the suboptimal optical characteristics associated with the standard CMOS fabrication process. The challenge at the system level is the development of monolithic readout architecture capable of supporting the large volume of dynamic traffic, associated with multiple single-photon pixels, without limiting the dynamic range and throughput of the sensor. Due to trade-offs in both functionality and performance, no general solution currently exists for an integrated single-photon sensor in standard CMOS single photon sensing and multi-photon resolution. The research described herein is directed towards the development of a versatile high performance integrated SPAD sensor in the standard CMOS process. Towards this purpose a SPAD device with elongated junction geometry and a perimeter field gate that features a large detection area and a highly reduced dark noise has been presented and characterized. Additionally, a novel front-end system for optimizing the dynamic range and after-pulsing noise of the pixel has been developed. The pixel is also equipped with an output interface with an adjustable pulse width response. In order to further enhance the effective dynamic range of the pixel a theoretical model for accurate dead time related loss compensation has been developed and verified. This thesis also introduces a new paradigm for electrical generation and encoding of the SPAD array response that supports fully digital operation at the pixel level while enabling dynamic discrete time amplitude encoding of the array response. Thus offering a first ever system solution to simultaneously exploit both the dynamic nature and the digital profile of the SPAD response. The array interface, comprising of multiple digital inputs capacitively coupled onto a shared quasi-floating sense node, in conjunction with the integrated digital decoding and readout electronics represents the first ever solid state single-photon sensor capable of both photon counting and photon number resolution. The viability of the readout architecture is demonstrated through simulations and preliminary proof of concept measurements

Current Programmed Active Pixel Sensors for Large Area Diagnostic X-ray Imaging

Rapid progress over the last decade on large area thin film transistor (TFT) arrays led to the emergence of high-performance, low-power, low-cost active matrix flat panel imagers. Despite the shortcomings associated with the instability and low mobility of TFTs, the amorphous silicon TFT technology still remains the primary solution for the backplane of flat panel imagers. The use of a-Si:H TFTs as the building block of the large area integrated circuit becomes challenging particularly when the role of the TFT is extended from traditional switching applications to on-pixel signal amplifier for large area digital imaging. This is the idea behind active pixel sensor (APS) architectures in which under each pixel an amplifier circuit consisting of one or two switching TFTs integrated with one amplifying TFT is fabricated. To take advantage of the full potential of these amplifiers, it is crucial to develop APS architectures to compensate for the limitations of the TFTs. In this thesis several APS architectures are designed, simulated, fabricated, and tested addressing these challenges using the mask sets presented in Appendix A. The proposed APS architectures can compensate for inherent stabilities of the comprising TFTs. Therefore, the sensitivity of their output data to the transistor variations is significantly suppressed. This is achieved by using a well defined external current source instead of the traditional voltage source to reset the APS architectures during the reset cycle of their periodic operation. The performance of these circuits is analyzed in terms of their stability, settling time, noise, and temperature-dependence. For appropriate readout of the current mode APS architectures, high gain transresistance amplifiers with correlated double sampling capability is designed, simulated and fabricated in CMOS technology. Measurement and measurement based calculation results reveal that the proposed APS architectures can meet even the stringent requirements of low noise, real-time digital fluoroscopy

An Optoelectronic Stimulator for Retinal Prosthesis

Retinal prostheses require the presence of viable population of cells in the inner retina. Evaluations of retina with Age-Related Macular Degeneration (AMD) and Retinitis Pigmentosa (RP) have shown a large number of cells remain in the inner retina compared with the outer retina. Therefore, vision loss caused by AMD and RP is potentially treatable with retinal prostheses. Photostimulation based retinal prostheses have shown many advantages compared with retinal implants. In contrary to electrode based stimulation, light does not require mechanical contact. Therefore, the system can be completely external and not does have the power and degradation problems of implanted devices. In addition, the stimulating point is flexible and does not require a prior decision on the stimulation location. Furthermore, a beam of light can be projected on tissue with both temporal and spatial precision. This thesis aims at fi nding a feasible solution to such a system. Firstly, a prototype of an optoelectronic stimulator was proposed and implemented by using the Xilinx Virtex-4 FPGA evaluation board. The platform was used to demonstrate the possibility of photostimulation of the photosensitized neurons. Meanwhile, with the aim of developing a portable retinal prosthesis, a system on chip (SoC) architecture was proposed and a wide tuning range sinusoidal voltage-controlled oscillator (VCO) which is the pivotal component of the system was designed. The VCO is based on a new designed Complementary Metal Oxide Semiconductor (CMOS) Operational Transconductance Ampli er (OTA) which achieves a good linearity over a wide tuning range. Both the OTA and the VCO were fabricated in the AMS 0.35 µm CMOS process. Finally a 9X9 CMOS image sensor with spiking pixels was designed. Each pixel acts as an independent oscillator whose frequency is controlled by the incident light intensity. The sensor was fabricated in the AMS 0.35 µm CMOS Opto Process. Experimental validation and measured results are provided