Fully-photonic digital radio over fibre for future super-broadband access network applications

This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel UniversityIn this thesis a Fully-Photonic DRoF (FP-DRoF) system is proposed for deploying of future super-broadband access networks. Digital Radio over Fibre (DRoF) is more independent of the fibre network impairments and the length of fibre than the ARoF link. In order for fully optical deployment of the signal conversion techniques in the FP-DRoF architecture, two key components an Analogue-to-Digital Converter (ADC) and a Digital-to-Analogue Converter (DAC)) for data conversion are designed and their performance are investigated whereas the physical functionality is evaluated. The system simulation results of the proposed pipelined Photonic ADC (PADC) show that the PADC has 10 GHz bandwidth around 60 GHz of sampling rate. Furthermore, by changing the bandwidth of the optical bandpass filter, switching to another band of sampling frequency provides optimised performance condition of the PADC. The PADC has low changes on the Effective Number of Bit (ENOB) response versus analogue RF input from 1 GHz up to 22 GHz for 60 GHz sampling frequency. The proposed 8-Bit pipelined PADC performance in terms of ENOB is evaluated at 60 Gigasample/s which is about 4.1. Recently, different methods have been reported by researchers to implement Photonic DACs (PDACs), but their aim was to convert digital electrical signals to the corresponding analogue signal by assisting the optical techniques. In this thesis, a Binary Weighted PDAC (BW-PDAC) is proposed. In this BW-PDAC, optical digital signals are fully optically converted to an analogue signal. The spurious free dynamic range at the output of the PDAC in a back-to-back deployment of the PADC and the PDAC was 26.6 dBc. For further improvement in the system performance, a 3R (Retiming, Reshaping and Reamplifying) regeneration system is proposed in this thesis. Simulation results show that for an ultrashort RZ pulse with a 5% duty cycle at 65 Gbit/s using the proposed 3R regeneration system on a link reduces rms timing jitter by 90% while the regenerated pulse eye opening height is improved by 65%. Finally, in this thesis the proposed FP-DRoF functionality is evaluated whereas its performance is investigated through a dedicated and shared fibre links. The simulation results show (in the case of low level signal to noise ratio, in comparison with ARoF through a dedicated fibre link) that the FP-DRoF has better BER performance than the ARoF in the order of 10-20. Furthermore, in order to realize a BER about 10-25 for the ARoF, the power penalty is about 4 dBm higher than the FP-DRoF link. The simulation results demonstrate that by considering 0.2 dB/km attenuation of a standard single mode fibre, the dedicated fibre length for the FP-DRoF link can be increased to about 20 km more than the ARoF link. Moreover, for performance assessment of the proposed FP-DRoF in a shared fibre link, the BER of the FP-DRoF link is about 10-10 magnitude less than the ARoF link for -19 dBm launched power into the fibre and the power penalty of the ARoF system is 10 dBm more than the FP-DRoF link. It is significant to increase the fibre link’s length of the FP-DRoF access network using common infrastructure. In addition, the simulation results are demonstrated that the FP-DRoF with non-uniform Wavelength Division Multiplexing (WDM) is more robust against four wave mixing impairment than the conventional WDM technique with uniform wavelength allocation and has better performance in terms of BER. It is clearly verified that the lunched power penalty at CS for DRoF link with uniform WDM techniques is about 2 dB higher than non-uniform WDM technique. Furthermore, uniform WDM method requires more bandwidth than non-uniform scheme which depends on the total number of channels and channels spacing

Power efficient analog-to-digital converters using both voltage and time domain information

As advanced wired and wireless communication systems attempt to achieve higher performance, the demand for high resolution and wide signal bandwidth in their associated ADCs is strongly increased. Recently, time-domain quantization has drawn attention from its scalability in deep submicron CMOS processes. Furthermore, there are several interesting aspects of time-domain quantizer by processing the signal in time rather than only in voltage domain especially for power efficiency. This research focuses on developing a new architecture for power efficient, high resolution ADCs using both voltage and time domain information. As a first approach, a new ΔƩ ADC based on a noise-shaped two-step integrating quantizer which quantizes the signal in voltage and time domains is presented. Attaining an extra order of noise-shaping from the integrating quantizer, the proposed ΔƩ ADC manifests a second-order noise-shaping with a first-order loop filter. Furthermore, this quantizer provides an 8b uantization in itself, drastically reducing the oversampling requirement. The proposed ADC also incorporates a new feedback DAC topology that alleviates the feedback DAC complexity of a two-step 8b quantizer. The measured results of the prototype ADC implemented in a 0.13μm CMOS demonstrate peak SNDR of 70.7dB (11.5b ENOB) at 8.1mW power, with an 8x OSR at 80MHz sampling frequency. To further improve ADC performance, a Nyquist ADC based on a time-based pipelined TDC is also proposed as a second approach. In this work, a simple V-T conversion scheme with a cheap low gain amplifier in its first stage and a hybrid time-domain quantization stage based on simple charge pump and capacitive DAC in its backend stages, are also proposed to improve ADC linearity and power efficiency. Using voltage and time domain information, the proposed ADC architecture is beneficial for both resolution and power efficiency, with MSBs resolved in voltage domain and LSBs in time domain. The measured results of the prototype ADC implemented in a 0.13μm CMOS demonstrate peak SNDR of 69.3dB (11.2b ENOB) at 6.38mW power and 70MHz sampling frequency. The FOM is 38.2fJ/conversion-step

An Ultra-Low-Power 75mV 64-Bit Current-Mode Majority-Function Adder

Ultra-low-power circuits are becoming more desirable due to growing portable device markets and they are also becoming more interesting and applicable today in biomedical, pharmacy and sensor networking applications because of the nano-metric scaling and CMOS reliability improvements. In this thesis, three main achievements are presented in ultra-low-power adders. First, a new majority function algorithm for carry and the sum generation is presented. Then with this algorithm and implied new architecture, we achieved a circuit with 75mV supply voltage operation. Last but not least, a 64 bit current-mode majority-function adder based on the new architecture and algorithm is successfully tested at 75mV supply voltage. The circuit consumed 4.5nW or 3.8pJ in one of the worst conditions

Low Power Circuits for Smart Flexible ECG Sensors

Cardiovascular diseases (CVDs) are the world leading cause of death. In-home heart condition monitoring effectively reduced the CVD patient hospitalization rate. Flexible electrocardiogram (ECG) sensor provides an affordable, convenient and comfortable in-home monitoring solution. The three critical building blocks of the ECG sensor i.e., analog frontend (AFE), QRS detector, and cardiac arrhythmia classifier (CAC), are studied in this research. A fully differential difference amplifier (FDDA) based AFE that employs DC-coupled input stage increases the input impedance and improves CMRR. A parasitic capacitor reuse technique is proposed to improve the noise/area efficiency and CMRR. An on-body DC bias scheme is introduced to deal with the input DC offset. Implemented in 0.35m CMOS process with an area of 0.405mm2, the proposed AFE consumes 0.9W at 1.8V and shows excellent noise effective factor of 2.55, and CMRR of 76dB. Experiment shows the proposed AFE not only picks up clean ECG signal with electrodes placed as close as 2cm under both resting and walking conditions, but also obtains the distinct -wave after eye blink from EEG recording. A personalized QRS detection algorithm is proposed to achieve an average positive prediction rate of 99.39% and sensitivity rate of 99.21%. The user-specific template avoids the complicate models and parameters used in existing algorithms while covers most situations for practical applications. The detection is based on the comparison of the correlation coefficient of the user-specific template with the ECG segment under detection. The proposed one-target clustering reduced the required loops. A continuous-in-time discrete-in-amplitude (CTDA) artificial neural network (ANN) based CAC is proposed for the smart ECG sensor. The proposed CAC achieves over 98% classification accuracy for 4 types of beats defined by AAMI (Association for the Advancement of Medical Instrumentation). The CTDA scheme significantly reduces the input sample numbers and simplifies the sample representation to one bit. Thus, the number of arithmetic operations and the ANN structure are greatly simplified. The proposed CAC is verified by FPGA and implemented in 0.18m CMOS process. Simulation results show it can operate at clock frequencies from 10KHz to 50MHz. Average power for the patient with 75bpm heart rate is 13.34W

The Fifth NASA Symposium on VLSI Design

The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design

Time resolved single photon imaging in Nanometer Scale CMOS technology

Time resolved imaging is concerned with the measurement of photon arrival time. It has a wealth of emerging applications including biomedical uses such as fluorescence lifetime microscopy and positron emission tomography, as well as laser ranging and imaging in three dimensions. The impact of time resolved imaging on human life is significant: it can be used to identify cancerous cells in-vivo, how well new drugs may perform, or to guide a robot around a factory or hospital. Two essential building blocks of a time resolved imaging system are a photon detector capable of sensing single photons, and fast time resolvers that can measure the time of flight of light to picosecond resolution. In order to address these emerging applications, miniaturised, single-chip, integrated arrays of photon detectors and time resolvers must be developed with state of the art performance and low cost. The goal of this research is therefore the design, layout and verification of arrays of low noise Single Photon Avalanche Diodes (SPADs) together with high resolution Time-Digital Converters (TDCs) using an advanced silicon fabrication process. The research reported in this Thesis was carried out as part of the E.U. funded Megaframe FP6 Project. A 32x32 pixel, one million frames per second, time correlated imaging device has been designed, simulated and fabricated using a 130nm CMOS Imaging process from ST Microelectronics. The imager array has been implemented together with required support cells in order to transmit data off chip at high speed as well as providing a means of device control, test and calibration. The fabricated imaging device successfully demonstrates the research objectives. The Thesis presents details of design, simulation and characterisation results of the elements of the Megaframe device which were the author’s own work. Highlights of the results include the smallest and lowest noise SPAD devices yet published for this class of fabrication process and an imaging array capable of recording single photon arrivals every microsecond, with a minimum time resolution of fifty picoseconds and single bit linearity

Advances in Solid State Circuit Technologies

This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields

Noise shaping techniques for analog and time to digital converters using voltage controlled oscillators

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.Includes bibliographical references (p. 175-181).Advanced CMOS processes offer very fast switching speed and high transistor density that can be utilized to implement analog signal processing functions in interesting and unconventional ways, for example by leveraging time as a signal domain. In this context, voltage controlled ring oscillators are circuit elements that are not only very attractive due to their highly digital implementation which takes advantage of scaling, but also due to their ability to amplify or integrate conventional voltage signals into the time domain. In this work, we take advantage of voltage controlled oscillators to implement analog- and time-to-digital converters with first-order quantization and mismatch noise-shaping. To implement a time-to-digital converter (TDC) with noise-shaping, we present a oscillator that is enabled during the measurement of an input, and then disabled in between measurements. By holding the state of the oscillator in between samples, the quantization error is saved and transferred to the following sample, which can be seen as first-order noise-shaping in the frequency domain. In order to achieve good noise shaping performance, we also present key details of a multi-path oscillator topology that is able to reduce the effective delay per stage by a factor of 5 and accurately preserve the quantization error from measurement to measurement. An 11-bit, 50Msps prototype time-to-digital converter (TDC) using a multi-path gated ring oscillator with 6ps of delay per stage demonstrates over 20dB of ist-order noise shaping. At frequencies below 1MHz, the TDC error integrates to 80fsrms for a dynamic range of 95dB with no calibration of differential non-linearity required. The 157x258pm TDC is realized in 0.13ipm CMOS and operates from a 1.5V supply.(cont.) The use of VCO-based quantization within continuous-time (CT) [Epsilon] [Delta] ADC structures is also explored, with a custom prototype in 0.13pm CMOS showing measured performance of 86/72dB SNR/SNDR with 10MHz bandwidth while consuming 40mW from a 1.2V supply and occupying an active area of 640pm X 660pm. A key element of the ADC structure is a 5-bit VCO-based quantizer clocked at 950 MHz which we show achieves first-order noise-shaping of its quantization noise. The quantizer structure allows the second order CT Epsilon] [Delta] ADC topology to achieve third order noise shaping, and direct connection of the VCO-based quantizer to the internal DACs of the ADC provides intrinsic dynamic element matching (DEM) of the DAC elements.by Matthew A. Z. Straayer.Ph.D

Trade-off analysis of modes of data handling for earth resources (ERS), volume 1

Data handling requirements are reviewed for earth observation missions along with likely technology advances. Parametric techniques for synthesizing potential systems are developed. Major tasks include: (1) review of the sensors under development and extensions of or improvements in these sensors; (2) development of mission models for missions spanning land, ocean, and atmosphere observations; (3) summary of data handling requirements including the frequency of coverage, timeliness of dissemination, and geographic relationships between points of collection and points of dissemination; (4) review of data routing to establish ways of getting data from the collection point to the user; (5) on-board data processing; (6) communications link; and (7) ground data processing. A detailed synthesis of three specific missions is included

Energy Efficient VLSI Circuits for MIMO-WLAN

Mobile communication - anytime, anywhere access to data and communication services - has been continuously increasing since the operation of the first wireless communication link by Guglielmo Marconi. The demand for higher data rates, despite the limited bandwidth, led to the development of multiple-input multiple-output (MIMO) communication which is often combined with orthogonal frequency division multiplexing (OFDM). Together, these two techniques achieve a high bandwidth efficiency. Unfortunately, techniques such as MIMO-OFDM significantly increase the signal processing complexity of transceivers. While fast improvements in the integrated circuit (IC) technology enabled to implement more signal processing complexity per chip, large efforts had and have to be done for novel algorithms as well as for efficient very large scaled integration (VLSI) architectures in order to meet today's and tomorrow's requirements for mobile wireless communication systems. In this thesis, we will present architectures and VLSI implementations of complete physical (PHY) layer application specific integrated circuits (ASICs) under the constraints imposed by an industrial wireless communication standard. Contrary to many other publications, we do not elaborate individual components of a MIMO-OFDM communication system stand-alone, but in the context of the complete PHY layer ASIC. We will investigate the performance of several MIMO detectors and the corresponding preprocessing circuits, being integrated into the entire PHY layer ASIC, in terms of achievable error-rate, power consumption, and area requirement. Finally, we will assemble the results from the proposed PHY layer implementations in order to enhance the energy efficiency of a transceiver. To this end, we propose a cross-layer optimization of PHY layer and medium access control (MAC) layer