Reliability-energy-performance optimisation in combinational circuits in presence of soft errors

PhD ThesisThe reliability metric has a direct relationship to the amount of value produced by a circuit, similar to the performance metric. With advances in CMOS technology, digital circuits become increasingly more susceptible to soft errors. Therefore, it is imperative to be able to assess and improve the level of reliability of these circuits. A framework for evaluating and improving the reliability of combinational circuits is proposed, and an interplay between the metrics of reliability, energy and performance is explored. Reliability evaluation is divided into two levels of characterisation: stochastic fault model (SFM) of the component library and a design-specific critical vector model (CVM). The SFM captures the properties of components with regard to the interference which causes error. The CVM is derived from a limited number of simulation runs on the specific design at the design time and producing the reliability metric. The idea is to move the high-complexity problem of the stochastic characterisation of components to the generic part of the design process, and to do it just once for a large number of specific designs. The method is demonstrated on a range of circuits with various structures. A three-way trade-off between reliability, energy, and performance has been discovered; this trade-off facilitates optimisations of circuits and their operating conditions. A technique for improving the reliability of a circuit is proposed, based on adding a slow stage at the primary output. Slow stages have the ability to absorb narrow glitches from prior stages, thus reducing the error probability. Such stages, or filters, suppress most of the glitches generated in prior stages and prevent them from arriving at the primary output of the circuit. Two filter solutions have been developed and analysed. The results show a dramatic improvement in reliability at the expense of minor performance and energy penalties. To alleviate the problem of the time-consuming analogue simulations involved in the proposed method, a simplification technique is proposed. This technique exploits the equivalence between the properties of the gates within a path and the equivalence between paths. On the basis of these equivalences, it is possible to reduce the number of simulation runs. The effectiveness of the proposed technique is evaluated by applying it to different circuits with a representative variety of path topologies. The results show a significant decrease in the time taken to estimate reliability at the expense of a minor decrease in the accuracy of estimation. The simplification technique enables the use of the proposed method in applications with complex circuits.Ministry of Education and Scientific Research in Liby

Analysis and Design of Resilient VLSI Circuits

The reliable operation of Integrated Circuits (ICs) has become increasingly difficult to achieve in the deep sub-micron (DSM) era. With continuously decreasing device feature sizes, combined with lower supply voltages and higher operating frequencies, the noise immunity of VLSI circuits is decreasing alarmingly. Thus, VLSI circuits are becoming more vulnerable to noise effects such as crosstalk, power supply variations and radiation-induced soft errors. Among these noise sources, soft errors (or error caused by radiation particle strikes) have become an increasingly troublesome issue for memory arrays as well as combinational logic circuits. Also, in the DSM era, process variations are increasing at an alarming rate, making it more difficult to design reliable VLSI circuits. Hence, it is important to efficiently design robust VLSI circuits that are resilient to radiation particle strikes and process variations. The work presented in this dissertation presents several analysis and design techniques with the goal of realizing VLSI circuits which are tolerant to radiation particle strikes and process variations. This dissertation consists of two parts. The first part proposes four analysis and two design approaches to address radiation particle strikes. The analysis techniques for the radiation particle strikes include: an approach to analytically determine the pulse width and the pulse shape of a radiation induced voltage glitch in combinational circuits, a technique to model the dynamic stability of SRAMs, and a 3D device-level analysis of the radiation tolerance of voltage scaled circuits. Experimental results demonstrate that the proposed techniques for analyzing radiation particle strikes in combinational circuits and SRAMs are fast and accurate compared to SPICE. Therefore, these analysis approaches can be easily integrated in a VLSI design flow to analyze the radiation tolerance of such circuits, and harden them early in the design flow. From 3D device-level analysis of the radiation tolerance of voltage scaled circuits, several non-intuitive observations are made and correspondingly, a set of guidelines are proposed, which are important to consider to realize radiation hardened circuits. Two circuit level hardening approaches are also presented to harden combinational circuits against a radiation particle strike. These hardening approaches significantly improve the tolerance of combinational circuits against low and very high energy radiation particle strikes respectively, with modest area and delay overheads. The second part of this dissertation addresses process variations. A technique is developed to perform sensitizable statistical timing analysis of a circuit, and thereby improve the accuracy of timing analysis under process variations. Experimental results demonstrate that this technique is able to significantly reduce the pessimism due to two sources of inaccuracy which plague current statistical static timing analysis (SSTA) tools. Two design approaches are also proposed to improve the process variation tolerance of combinational circuits and voltage level shifters (which are used in circuits with multiple interacting power supply domains), respectively. The variation tolerant design approach for combinational circuits significantly improves the resilience of these circuits to random process variations, with a reduction in the worst case delay and low area penalty. The proposed voltage level shifter is faster, requires lower dynamic power and area, has lower leakage currents, and is more tolerant to process variations, compared to the best known previous approach. In summary, this dissertation presents several analysis and design techniques which significantly augment the existing work in the area of resilient VLSI circuit design

Empirical timing analysis of CPUs and delay fault tolerant design using partial redundancy

The operating clock frequency is determined by the longest signal propagation delay, setup/hold time, and timing margin. These are becoming less predictable with the increasing design complexity and process miniaturization. The difficult challenge is then to ensure that a device operating at its clock frequency is error-free with quantifiable assurance. Effort at device-level engineering will not suffice for these circuits exhibiting wide process variation and heightened sensitivities to operating condition stress. Logic-level redress of this issue is a necessity and we propose a design-level remedy for this timing-uncertainty problem. The aim of the design and analysis approaches presented in this dissertation is to provide framework, SABRE, wherein an increased operating clock frequency can be achieved. The approach is a combination of analytical modeling, experimental analy- sis, hardware /time-redundancy design, exception handling and recovery techniques. Our proposed design replicates only a necessary part of the original circuit to avoid high hardware overhead as in triple-modular-redundancy (TMR). The timing-critical combinational circuit is path-wise partitioned into two sections. The combinational circuits associated with long paths are laid out without any intrusion except for the fan-out connections from the first section of the circuit to a replicated second section of the combinational circuit. Thus only the second section of the circuit is replicated. The signals fanning out from the first section are latches, and thus are far shorter than the paths spanning the entire combinational circuit. The replicated circuit is timed at a subsequent clock cycle to ascertain relaxed timing paths. This insures that the likelihood of mistiming due to stress or process variation is eliminated. During the subsequent clock cycle, the outcome of the two logically identical, yet time-interleaved, circuit outputs are compared to detect faults. When a fault is detected, the retry sig- nal is triggered and the dynamic frequency-step-down takes place before a pipe flush, and retry is issued. The significant timing overhead associated with the retry is offset by the rarity of the timing violation events. Simulation results on ISCAS Benchmark circuits show that 10% of clock frequency gain is possible with 10 to 20 % of hardware overhead of replicated timing-critical circuit

Power Estimation Technique for DSP Architectures.

The main goal of power estimation is to optimize the power consumption of a electronic design. Power is a strongly pattern dependent function. Input statistics greatly influence on average power. We solve the pattern dependence problem for intellectual property (IP) designs. In this paper, we present a power macro-modeling technique for digital signal processing (DSP) architectures in terms of the statistical knowledge of their primary inputs. During the power estimation procedure, the sequence of an input stream is generated by a genetic algorithm using input metrics. Then, a Monte Carlo zero delay simulation is performed and a power dissipation macro-model function is built from power dissipation results. From then on, this macro-model function can be used to estimate power dissipation of the system just by using the statistics of the macro-block’s primary in puts. In experiments with the DSP system, the average error is 26%

Efeitos da falha lógica e fuga (dissipação de energia de área) em sistemas criptográficos usando a técnica de clock gating para aprimorar o protocolo na web

The last century has seen an evolution in technology that has improved communication systems and, in general, made life easier for people. Our communication systems have become faster and more dependable as a result of the explosion of gadgets and services. But, these upgrades come at a price. The power consumption is one of the most worrying costs. In recent years, the solution involved installing larger, more powerful batteries—so long as doing so did not limit mobility. Today's economic and environmental problems compel us to consider alternative solutions, like methods for lowering the power consumption of digital devices. This study focuses on using digital circuits, which promise to deliver good energy efficiency and desirable performance at very low voltage savings. Certain digital switches are allegedly redundant and not required for the circuit to function properly, yet they continue to use energy. So, one of the primary issues for low power design is reducing such redundant switches. Subthreshold conduction in digital circuits is typically seen as a “parasitic” leakage in a condition where there should ideally be no conduction. Sub-threshold activities thereby reduce the problem of lowering power consumption, but do so at the expense of system throughput deterioration, fluctuations in system stability and functionality, temperature variations, and most critically, design space utilization. In order to minimize some of these redundant switches and to make circuits more energy-efficient while maintaining functionality, this study suggests two novel techniques. It uses an optimization method based on threshold voltage change to reduce glitch power. A glitch-free circuit netlist is created using an algorithm, while still maintaining the requisite delay performance. Using this approach results in a 6.14% overall reduction in energy consumption.El siglo pasado fue testigo de una evolución de la tecnología que mejoró los sistemas de comunicación y, en general, facilitó la vida de las personas. Nuestros sistemas de comunicación se han vuelto más rápidos y confiables como resultado de la explosión de dispositivos y servicios. Pero, estas actualizaciones tienen un precio. El consumo de energía es uno de los costes más preocupantes. En los últimos años, la solución ha pasado por instalar baterías más grandes y potentes, siempre que esto no limite la movilidad. Los problemas económicos y ambientales actuales nos obligan a considerar soluciones alternativas, como métodos para reducir el consumo de energía de los dispositivos digitales. Este estudio se centra en el uso de circuitos digitales, que prometen ofrecer una buena eficiencia energética y un rendimiento deseable con un ahorro de tensión muy bajo. Se supone que ciertos interruptores digitales son redundantes y no necesarios para que el circuito funcione correctamente, pero continúan consumiendo energía. Por lo tanto, uno de los principales problemas para el diseño de bajo consumo es reducir estos conmutadores redundantes. La conducción por debajo del umbral en los circuitos digitales normalmente se considera una fuga “parásita” en una condición en la que, idealmente, no debería haber conducción. Por lo tanto, las actividades por debajo del umbral reducen el problema de disminuir el consumo de energía, pero lo hacen a expensas del deterioro del rendimiento del sistema, las fluctuaciones en la estabilidad y funcionalidad del sistema, las variaciones de temperatura y, lo que es más importante, la utilización del espacio de diseño. Para minimizar algunos de estos interruptores redundantes y hacer que los circuitos sean más eficientes desde el punto de vista energético manteniendo la funcionalidad, este estudio sugiere dos nuevas técnicas. Utiliza un método de optimización basado en cambiar el voltaje de umbral para reducir la energía de falla. Se crea una lista de conexiones de circuito impecable utilizando un algoritmo mientras se mantiene el rendimiento de retardo requerido. El uso de este enfoque da como resultado una reducción general del 6,14 % en el consumo de energía.O último século assistiu a uma evolução da tecnologia que melhorou os sistemas de comunicação e, em geral, facilitou a vida das pessoas. Nossos sistemas de comunicação tornaram-se mais rápidos e confiáveis como resultado da explosão de aparelhos e serviços. Mas, essas atualizações têm um preço. O consumo de energia é um dos custos mais preocupantes. Nos últimos anos, a solução envolveu a instalação de baterias maiores e mais potentes, desde que isso não limitasse a mobilidade. Os problemas econômicos e ambientais de hoje nos obrigam a considerar soluções alternativas, como métodos para reduzir o consumo de energia de dispositivos digitais. Este estudo se concentra no uso de circuitos digitais, que prometem oferecer boa eficiência energética e desempenho desejável com economia de tensão muito baixa. Certos interruptores digitais são supostamente redundantes e não são necessários para o funcionamento adequado do circuito, mas continuam a consumir energia. Portanto, um dos principais problemas para o projeto de baixo consumo de energia é reduzir esses switches redundantes. A condução abaixo do limiar em circuitos digitais é normalmente vista como uma fuga “parasita” em uma condição em que idealmente não deveria haver condução. As atividades abaixo do limite reduzem, assim, o problema de diminuir o consumo de energia, mas o fazem às custas da deterioração da taxa de transferência do sistema, flutuações na estabilidade e funcionalidade do sistema, variações de temperatura e, mais criticamente, utilização do espaço de projeto. A fim de minimizar alguns desses switches redundantes e tornar os circuitos mais eficientes em termos de energia, mantendo a funcionalidade, este estudo sugere duas novas técnicas. Ele usa um método de otimização baseado na mudança de tensão limite para reduzir a energia de falha. Uma netlist de circuito sem falhas é criada usando um algoritmo, mantendo o desempenho de atraso necessário. O uso dessa abordagem resulta em uma redução geral de 6,14% no consumo de energia

Fast and accurate SER estimation for large combinational blocks in early stages of the design

Soft Error Rate (SER) estimation is an important challenge for integrated circuits because of the increased vulnerability brought by technology scaling. This paper presents a methodology to estimate in early stages of the design the susceptibility of combinational circuits to particle strikes. In the core of the framework lies MASkIt , a novel approach that combines signal probabilities with technology characterization to swiftly compute the logical, electrical, and timing masking effects of the circuit under study taking into account all input combinations and pulse widths at once. Signal probabilities are estimated applying a new hybrid approach that integrates heuristics along with selective simulation of reconvergent subnetworks. The experimental results validate our proposed technique, showing a speedup of two orders of magnitude in comparison with traditional fault injection estimation with an average estimation error of 5 percent. Finally, we analyze the vulnerability of the Decoder, Scheduler, ALU, and FPU of an out-of-order, superscalar processor design.This work has been partially supported by the Spanish Ministry of Economy and Competitiveness and Feder Funds under grant TIN2013-44375-R, by the Generalitat de Catalunya under grant FI-DGR 2016, and by the FP7 program of the EU under contract FP7-611404 (CLERECO).Peer ReviewedPostprint (author's final draft

Reliability Modeling and Analysis of Clockless Wave Pipeline Core for Embedded Combinational Logic Design

This paper presents a model for analyzing the reliability of a clockless wave pipeline as an intellectual property (IP) core for embedded design. This design requires different clocking requirements by each embedded IP core during integration. Therefore, either partial or global lack of synchronization of the embedded clocking is considered for the data flow. The clockless wave pipeline represents an alternative to a traditional pipeline scheme; it requires an innovative computing model that is readily suitable for high-throughput computing by heterogeneous IP logic cores embedded in system-on-chip (SoC). A clockless wave pipeline technique relies on local asynchronous operation for seamless integration of a combinational core into an SoC. The basic computational components of a clockless wave pipeline are the datawaves, together with the request signals and switches. The coordination of the processing of the datawaves throughout the pipeline by the request signals is accomplished with no intermediate access in the clock control. Furthermore, the reliability of clockless-wave-pipeline-based cores is of importance when designing a reliable SOC. In this paper, the reliability in the clockless operations of the wave pipeline is analyzed by considering the datawaves and the request signals. The effect of the so-called out-of-orchestration between the datawaves and the request signals (which is referred to as a datawave fault) is proposed in the reliability analysis. A clockless-induced datawave fault model is proposed for clockless fault-tolerant design

Utilizing the Digital Fingerprint Method for Secure Key Generation

This research examines a new way to generate an uncloneable secure key by taking advantage of the delay characteristics of individual transistors. The user profiles the circuit to deduce the glitch count of each output line for each number of selectable buffers added to the circuit. The user can then use this information to generate a specific glitch count on each output line, which is passed to an encryption algorithm as its key. The results detail tests of two configurations for adding a selectable amount of buffers into each glitch circuit in order to induce additional delay. One configuration adds up to seven buffers that is equivalent to the binary digits used on the three SELECT lines of a multiplexer. The second, referred to as the cascaded design, has eight different quantities of selectable buffers, but they all connect to one multiplexer. Each successive line connects to the previous line and adds a certain number of buffers. The linear selection implementation produces almost 15% more usable output lines over the cascaded design, where a usable line is defined as one that has at least one ‘1’ and one ‘0’ glitch count in response to every buffer count. Tests were also performed to determine the optimal number of buffers added to each output using the linear buffer selection configuration. Using three input bits to the buffer unit produced 30.94% usable outputs. Four bits generated nearly 25% more usable outputs, while the use of six bits gave less than a 5% improvement over four bits. The average repeatability of the glitch count is 94.85% using this method. The overall distinguishability of the generated glitch counts for each output line is 10.46%