Parity space-based fault detection for Markovian jump systems

This article deals with problems of parity space-based fault detection for a class of discrete-time linear Markovian jump systems. A new algorithm is firstly introduced to reduce the computation of mode-dependent redundancy relation parameter matrices. Different from the case of linear time invariant systems, the parity space-based residual generator for a Markovian jump system cannot be designed off-line because it depends on the history of system modes in the last finite steps. In order to overcome this difficulty, a finite set of parity matrices is pre-designed applying a unified approach to linear time invariant systems. Then the on-line residual generation can be easily implemented. Moreover, the problem of residual evaluation is also considered which includes the determination of a residual evaluation function and a threshold. Finally, a numerical example is given to illustrate the effectiveness of the proposed method

A comparative analysis of fault detection schemes for stochastic continuous-time dynamical systems

This paper addresses a comparative analysis of the existing schemes for fault detection in continuous-time stochastic dynamical systems. Such schemes prove to be efficient when dealing with specific types of fault functions; on the other hand, they show very different performance sensitivity when dealing with new fault profiles and system noise. The study suggests the use of a combined scheme, supervised by a high level decision rule set

Optical Quantum Computation

We review the field of Optical Quantum Computation, considering the various implementations that have been proposed and the experimental progress that has been made toward realizing them. We examine both linear and nonlinear approaches and both particle and field encodings. In particular we discuss the prospects for large scale optical quantum computing in terms of the most promising physical architectures and the technical requirements for realizing them

Self-checking on-line testable static RAM

This is a fault-tolerant random access memory for use in fault-tolerant computers. It comprises a plurality of memory chips each comprising a plurality of on-line testable and correctable memory cells disposed in rows and columns for holding individually addressable binary bits and provision for error detection incorporated into each memory cell for outputting an error signal whenever a transient error occurs therein. In one embodiment, each of the memory cells comprises a pair of static memory sub-cells for simultaneously receiving and holding a common binary data bit written to the memory cell and the error detection provision comprises comparator logic for continuously sensing and comparing the contents of the memory sub-cells to one another and for outputting the error signal whenever the contents do not match. In another embodiment, each of the memory cells comprises a static memory sub-cell and a dynamic memory sub-cell for simultaneously receiving and holding a common binary data bit written to the memory cell and the error detection provision comprises comparator logic for continuously sensing and comparing the contents of the static memory sub-cell to the dynamic memory sub-cell and for outputting the error signal whenever the contents do not match. Capability for correction of errors is also included

Fault-tolerant computer study

A set of building block circuits is described which can be used with commercially available microprocessors and memories to implement fault tolerant distributed computer systems. Each building block circuit is intended for VLSI implementation as a single chip. Several building blocks and associated processor and memory chips form a self checking computer module with self contained input output and interfaces to redundant communications buses. Fault tolerance is achieved by connecting self checking computer modules into a redundant network in which backup buses and computer modules are provided to circumvent failures. The requirements and design methodology which led to the definition of the building block circuits are discussed

Practical effects in the preparation of cluster states using weak non-linearities

We discuss experimental effects in the implementation of a recent scheme for performing bus mediated entangling operations between qubits. Here a bus mode, a strong coherent state, successively undergoes weak Kerr-type non-linear interactions with qubits. A quadrature measurement on the bus then projects the qubits into an entangled state. This approach has the benefit that entangling gates are non-destructive, may be performed non-locally, and there is no need for efficient single photon detection. In this paper we examine practical issues affecting its experimental implementation. In particular, we analyze the effects of post-selection errors, qubit loss, bus loss, mismatched coupling rates and mode-mismatch. We derive error models for these effects and relate them to realistic fault-tolerant thresholds, providing insight into realistic experimental requirements.Comment: 8 pages, 5 figure

Study of fault tolerant software technology for dynamic systems

The major aim of this study is to investigate the feasibility of using systems-based failure detection isolation and compensation (FDIC) techniques in building fault-tolerant software and extending them, whenever possible, to the domain of software fault tolerance. First, it is shown that systems-based FDIC methods can be extended to develop software error detection techniques by using system models for software modules. In particular, it is demonstrated that systems-based FDIC techniques can yield consistency checks that are easier to implement than acceptance tests based on software specifications. Next, it is shown that systems-based failure compensation techniques can be generalized to the domain of software fault tolerance in developing software error recovery procedures. Finally, the feasibility of using fault-tolerant software in flight software is investigated. In particular, possible system and version instabilities, and functional performance degradation that may occur in N-Version programming applications to flight software are illustrated. Finally, a comparative analysis of N-Version and recovery block techniques in the context of generic blocks in flight software is presented