Algorithm Development and VLSI Implementation of Energy Efficient Decoders of Polar Codes

With its low error-floor performance, polar codes attract significant attention as the potential standard error correction code (ECC) for future communication and data storage. However, the VLSI implementation complexity of polar codes decoders is largely influenced by its nature of in-series decoding. This dissertation is dedicated to presenting optimal decoder architectures for polar codes. This dissertation addresses several structural properties of polar codes and key properties of decoding algorithms that are not dealt with in the prior researches. The underlying concept of the proposed architectures is a paradigm that simplifies and schedules the computations such that hardware is simplified, latency is minimized and bandwidth is maximized. In pursuit of the above, throughput centric successive cancellation (TCSC) and overlapping path list successive cancellation (OPLSC) VLSI architectures and express journey BP (XJBP) decoders for the polar codes are presented. An arbitrary polar code can be decomposed by a set of shorter polar codes with special characteristics, those shorter polar codes are referred to as constituent polar codes. By exploiting the homogeneousness between decoding processes of different constituent polar codes, TCSC reduces the decoding latency of the SC decoder by 60% for codes with length n = 1024. The error correction performance of SC decoding is inferior to that of list successive cancellation decoding. The LSC decoding algorithm delivers the most reliable decoding results; however, it consumes most hardware resources and decoding cycles. Instead of using multiple instances of decoding cores in the LSC decoders, a single SC decoder is used in the OPLSC architecture. The computations of each path in the LSC are arranged to occupy the decoder hardware stages serially in a streamlined fashion. This yields a significant reduction of hardware complexity. The OPLSC decoder has achieved about 1.4 times hardware efficiency improvement compared with traditional LSC decoders. The hardware efficient VLSI architectures for TCSC and OPLSC polar codes decoders are also introduced. Decoders based on SC or LSC algorithms suffer from high latency and limited throughput due to their serial decoding natures. An alternative approach to decode the polar codes is belief propagation (BP) based algorithm. In BP algorithm, a graph is set up to guide the beliefs propagated and refined, which is usually referred to as factor graph. BP decoding algorithm allows decoding in parallel to achieve much higher throughput. XJBP decoder facilitates belief propagation by utilizing the specific constituent codes that exist in the conventional factor graph, which results in an express journey (XJ) decoder. Compared with the conventional BP decoding algorithm for polar codes, the proposed decoder reduces the computational complexity by about 40.6%. This enables an energy-efficient hardware implementation. To further explore the hardware consumption of the proposed XJBP decoder, the computations scheduling is modeled and analyzed in this dissertation. With discussions on different hardware scenarios, the optimal scheduling plans are developed. A novel memory-distributed micro-architecture of the XJBP decoder is proposed and analyzed to solve the potential memory access problems of the proposed scheduling strategy. The register-transfer level (RTL) models of the XJBP decoder are set up for comparisons with other state-of-the-art BP decoders. The results show that the power efficiency of BP decoders is improved by about 3 times

Algorithm Development and VLSI Implementation of Energy Efficient Decoders of Polar Codes

With its low error-floor performance, polar codes attract significant attention as the potential standard error correction code (ECC) for future communication and data storage. However, the VLSI implementation complexity of polar codes decoders is largely influenced by its nature of in-series decoding. This dissertation is dedicated to presenting optimal decoder architectures for polar codes. This dissertation addresses several structural properties of polar codes and key properties of decoding algorithms that are not dealt with in the prior researches. The underlying concept of the proposed architectures is a paradigm that simplifies and schedules the computations such that hardware is simplified, latency is minimized and bandwidth is maximized. In pursuit of the above, throughput centric successive cancellation (TCSC) and overlapping path list successive cancellation (OPLSC) VLSI architectures and express journey BP (XJBP) decoders for the polar codes are presented. An arbitrary polar code can be decomposed by a set of shorter polar codes with special characteristics, those shorter polar codes are referred to as constituent polar codes. By exploiting the homogeneousness between decoding processes of different constituent polar codes, TCSC reduces the decoding latency of the SC decoder by 60% for codes with length n = 1024. The error correction performance of SC decoding is inferior to that of list successive cancellation decoding. The LSC decoding algorithm delivers the most reliable decoding results; however, it consumes most hardware resources and decoding cycles. Instead of using multiple instances of decoding cores in the LSC decoders, a single SC decoder is used in the OPLSC architecture. The computations of each path in the LSC are arranged to occupy the decoder hardware stages serially in a streamlined fashion. This yields a significant reduction of hardware complexity. The OPLSC decoder has achieved about 1.4 times hardware efficiency improvement compared with traditional LSC decoders. The hardware efficient VLSI architectures for TCSC and OPLSC polar codes decoders are also introduced. Decoders based on SC or LSC algorithms suffer from high latency and limited throughput due to their serial decoding natures. An alternative approach to decode the polar codes is belief propagation (BP) based algorithm. In BP algorithm, a graph is set up to guide the beliefs propagated and refined, which is usually referred to as factor graph. BP decoding algorithm allows decoding in parallel to achieve much higher throughput. XJBP decoder facilitates belief propagation by utilizing the specific constituent codes that exist in the conventional factor graph, which results in an express journey (XJ) decoder. Compared with the conventional BP decoding algorithm for polar codes, the proposed decoder reduces the computational complexity by about 40.6%. This enables an energy-efficient hardware implementation. To further explore the hardware consumption of the proposed XJBP decoder, the computations scheduling is modeled and analyzed in this dissertation. With discussions on different hardware scenarios, the optimal scheduling plans are developed. A novel memory-distributed micro-architecture of the XJBP decoder is proposed and analyzed to solve the potential memory access problems of the proposed scheduling strategy. The register-transfer level (RTL) models of the XJBP decoder are set up for comparisons with other state-of-the-art BP decoders. The results show that the power efficiency of BP decoders is improved by about 3 times

LDPC code-based bandwidth efficient coding schemes for wireless communications

This dissertation deals with the design of bandwidth-efficient coding schemes with Low-Density Parity-Check (LDPC) for reliable wireless communications. Code design for wireless channels roughly falls into three categories: (1) when channel state information (CSI) is known only to the receiver (2) more practical case of partial CSI at the receiver when the channel has to be estimated (3) when CSI is known to the receiver as well as the transmitter. We consider coding schemes for all the above categories. For the first scenario, we describe a bandwidth efficient scheme which uses highorder constellations such as QAM over both AWGN as well as fading channels. We propose a simple design with LDPC codes which combines the good properties of Multi-level Coding (MLC) and bit-interleaved coded-modulation (BICM) schemes. Through simulations, we show that the proposed scheme performs better than MLC for short-medium lengths on AWGN and block-fading channels. For the first case, we also characterize the rate-diversity tradeoff of MIMO-OFDM and SISO-OFDM systems. We design optimal coding schemes which achieve this tradeoff when transmission is from a constrained constellation. Through simulations, we show that with a sub-optimal iterative decoder, the performance of this coding scheme is very close to the optimal limit for MIMO (flat quasi-static fading), MIMO-OFDM and SISO OFDM systems. For the second case, we design non-systematic Irregular Repeat Accumulate (IRA) codes, which are a special class of LDPC codes, for Inter-Symbol Interference (ISI) fading channels when CSI is estimated at the receiver. We use Orthogonal Frequency Division Multiplexing (OFDM) to convert the ISI fading channel into parallel flat fading subchannels. We use a simple receiver structure that performs iterative channel estimation and decoding and use non-systematic IRA codes that are optimized for this receiver. This combination is shown to perform very close to a receiver with perfect CSI and is also shown to be robust to change in the number of channel taps and Doppler. For the third case, we look at bandwidth efficient schemes for fading channels that perform close to capacity when the channel state information is known at the transmitter as well as the receiver. Schemes that achieve capacity with a Gaussian codebook for the above system are already known but not for constrained constellations. We derive the near-optimum scheme to achieve capacity with constrained constellations and then propose coding schemes which perform close to capacity. Through linear transformations, a MIMO system can be converted into non-interfering parallel subchannels and we further extend the proposed coding schemes to the MIMO case too

Decoding of Decode and Forward (DF) Relay Protocol using Min-Sum Based Low Density Parity Check (LDPC) System

Decoding high complexity is a major issue to design a decode and forward (DF) relay protocol. Thus, the establishment of low complexity decoding system would beneficial to assist decode and forward relay protocol. This paper reviews existing methods for the min-sum based LDPC decoding system as the low complexity decoding system. Reference lists of chosen articles were further reviewed for associated publications. This paper introduces comprehensive system model representing and describing the methods developed for LDPC based for DF relay protocol. It is consists of a number of components: (1) encoder and modulation at the source node, (2) demodulation, decoding, encoding and modulation at relay node, and (3) demodulation and decoding at the destination node. This paper also proposes a new taxonomy for min-sum based LDPC decoding techniques, highlights some of the most important components such as data used, result performances and profiles the Variable and Check Node (VCN) operation methods that have the potential to be used in DF relay protocol. Min-sum based LDPC decoding methods have the potential to provide an objective measure the best tradeoff between low complexities decoding process and the decoding error performance, and emerge as a cost-effective solution for practical application

Bandwidth-efficient communication systems based on finite-length low density parity check codes

Low density parity check (LDPC) codes are linear block codes constructed by pseudo-random parity check matrices. These codes are powerful in terms of error performance and, especially, have low decoding complexity. While infinite-length LDPC codes approach the capacity of communication channels, finite-length LDPC codes also perform well, and simultaneously meet the delay requirement of many communication applications such as voice and backbone transmissions. Therefore, finite-length LDPC codes are attractive to employ in low-latency communication systems. This thesis mainly focuses on the bandwidth-efficient communication systems using finite-length LDPC codes. Such bandwidth-efficient systems are realized by mapping a group of LDPC coded bits to a symbol of a high-order signal constellation. Depending on the systems' infrastructure and knowledge of the channel state information (CSI), the signal constellations in different coded modulation systems can be two-dimensional multilevel/multiphase constellations or multi-dimensional space-time constellations. In the first part of the thesis, two basic bandwidth-efficient coded modulation systems, namely LDPC coded modulation and multilevel LDPC coded modulation, are investigated for both additive white Gaussian noise (AWGN) and frequency-flat Rayleigh fading channels. The bounds on the bit error rate (BER) performance are derived for these systems based on the maximum likelihood (ML) criterion. The derivation of these bounds relies on the union bounding and combinatoric techniques. In particular, for the LDPC coded modulation, the ML bound is computed from the Hamming distance spectrum of the LDPC code and the Euclidian distance profile of the two-dimensional constellation. For the multilevel LDPC coded modulation, the bound of each decoding stage is obtained for a generalized multilevel coded modulation, where more than one coded bit is considered for level. For both systems, the bounds are confirmed by the simulation results of ML decoding and/or the performance of the ordered-statistic decoding (OSD) and the sum-product decoding. It is demonstrated that these bounds can be efficiently used to evaluate the error performance and select appropriate parameters (such as the code rate, constellation and mapping) for the two communication systems.The second part of the thesis studies bandwidth-efficient LDPC coded systems that employ multiple transmit and multiple receive antennas, i.e., multiple-input multiple-output (MIMO) systems. Two scenarios of CSI availability considered are: (i) the CSI is unknown at both the transmitter and the receiver; (ii) the CSI is known at both the transmitter and the receiver. For the first scenario, LDPC coded unitary space-time modulation systems are most suitable and the ML performance bound is derived for these non-coherent systems. To derive the bound, the summation of chordal distances is obtained and used instead of the Euclidean distances. For the second case of CSI, adaptive LDPC coded MIMO modulation systems are studied, where three adaptive schemes with antenna beamforming and/or antenna selection are investigated and compared in terms of the bandwidth efficiency. For uncoded discrete-rate adaptive modulation, the computation of the bandwidth efficiency shows that the scheme with antenna selection at the transmitter and antenna combining at the receiver performs the best when the number of antennas is small. For adaptive LDPC coded MIMO modulation systems, an achievable threshold of the bandwidth efficiency is also computed from the ML bound of LDPC coded modulation derived in the first part

Design and Evaluation of the Efficiency of Channel Coding LDPC Codes for 5G Information Technology

This paper proposes a result of an investigation of a topical problem and the development of models for efficient coding in information networks based on codes with a low density of parity check. The main advantage of the technique is the presented recommendations for choosing a signal-code construction is carried out taking into account the code rate and the number of iterations decoding for envisaging the defined noise immunity indices. The noise immunity of signal-code constructions based on low-density codes has been increased by combining them with multi position digital modulation. This solution eventually allowed to develop a strategy for decoder designing of such codes and to optimize the code structure for a specific information network. To test the effectiveness of the proposed method, MATLAB simulations are carried out under for various Information channels binary symmetric channel (BSC), a channel with additive white Gaussian noise (AWGN), binary asymmetric channel (BAC), asymmetric channel Z type. In addition, different code rates were used during the experiment. The study of signal-code constructions with differential modulation is presented. The efficiency of different decoding algorithms is investigated. The advantage of the obtained results over the known ones consists in determining the maximum noise immunity for the proposed codes. The energy gain was on the order of 6 dB, and an increase in the number of decoding iterations from 3 to 10 leads to a gain in coding energy of 5 dB. Envisaged that the results obtained can be very useful in the development of practical coding schemes in 5G networks

Design and implementation of log domain decoder

Low-Density-Parity-Check (LDPC) code has become famous in communications systems for error correction, as an advantage of the robust performance in correcting errors and the ability to meet all the requirements of the 5G system. However, the mot challenge faced researchers is the hardware implementation, because of higher complexity and long run-time. In this paper, an efficient and optimum design for log domain decoder has been implemented using Xilinx system generator with FPGA device Kintex 7 (XC7K325T-2FFG900C). Results confirm that the proposed decoder gives a Bit Error Rate (BER) very closed to theory calculations which illustrate that this decoder is suitable for next generation demand which needs high data rate with very low BER

LDPC-coded modulation for transmission over AWGN and flat rayleigh fading channels

La modulation codée est une technique de transmission efficace en largeur de bande qui intègre le codage de canal et la modulation en une seule entité et ce, afin d'améliorer les performances tout en conservant la même efficacité spectrale comparé à la modulation non codée. Les codes de parité à faible densité (low-density parity-check codes, LDPC) sont les codes correcteurs d'erreurs les plus puissants et approchent la limite de Shannon, tout en ayant une complexité de décodage relativement faible. L'idée de combiner les codes LDPC et la modulation efficace en largeur de bande a donc été considérée par de nombreux chercheurs. Dans ce mémoire, nous étudions une méthode de modulation codée à la fois puissante et efficace en largeur de bande, ayant d'excellentes performances de taux d'erreur binaire et une complexité d'implantation faible. Ceci est réalisé en utilisant un encodeur rapide, un décoder de faible complexité et aucun entrelaceur. Les performances du système proposé pour des transmissions sur un canal additif gaussien blanc et un canal à évanouissements plats de Rayleigh sont évaluées au moyen de simulations. Les résultats numériques montrent que la méthode de modulation codée utilisant la modulation d'amplitude en quadrature à M niveaux (M-QAM) peut atteindre d'excellentes performances pour toute une gamme d'efficacité spectrale. Une autre contribution de ce mémoire est une méthode simple pour réaliser une modulation codée adaptative avec les codes LDPC pour la transmission sur des canaux à évanouissements plats et lents de Rayleigh. Dans cette méthode, six combinaisons de paires encodeur modulateur sont employées pour une adaptation trame par trame. L'efficacité spectrale moyenne varie entre 0.5 et 5 bits/s/Hz lors de la transmission. Les résultats de simulation montrent que la modulation codée adaptative avec les codes LDPC offre une meilleure efficacité spectrale tout en maintenant une performance d'erreur acceptable