Design for testability method at register transfer level

The testing of sequential circuit is more complex compared to combinational circuit because it needs a sequence of vectors to detect a fault. Its test cost increases with the complexity of the sequential circuit-under-test (CUT). Thus, design for testability (DFT) concept has been introduced to reduce testing complexity, as well as to improve testing effectiveness and efficiency. Scan technique is one of the mostly used DFT method. However, it has cost overhead in terms of area due to the number of added multiplexers for each flip-flop, and test application time due to shifting of test patterns. This research is motivated to introduce non-scan DFT method at register transfer level (RTL) in order to reduce test cost. DFT at RTL level is done based on functional information of the CUT and the connectivity of CUT registers. The process of chaining a register to another register is more effective in terms of area overhead and test application time. The first contribution of this work is the introduction of a non-scan DFT method at the RTL level that considers the information of controllability and observability of CUT that can be extracted from RTL description. It has been proven through simulation that the proposed method has higher fault coverage of around 90%, shorter test application time, shorter test generation time and 10% reduction in area overhead compared to other methods in literature for most benchmark circuits. The second contribution of this work is the introduction of built-in self-test (BIST) method at the RTL level which uses multiple input signature registers (MISRs) as BIST components instead of concurrent built-in logic block observers (CBILBOs). The selection of MISR as test register is based on extended minimum feedback vertex set algorithm. This new BIST method results in lower area overhead by about 32.9% and achieves similar higher fault coverage compared to concurrent BIST method. The introduction of non-scan DFT at the RTL level is done before logic synthesis process. Thus, the testability violations can be fixed without repeating the logic synthesis process during DFT insertion at the RTL level

Shuttle Ground Operations Efficiencies/Technologies (SGOE/T) study. Volume 2: Ground Operations evaluation

The Ground Operations Evaluation describes the breath and depth of the various study elements selected as a result of an operational analysis conducted during the early part of the study. Analysis techniques used for the evaluation are described in detail. Elements selected for further evaluation are identified; the results of the analysis documented; and a follow-on course of action recommended. The background and rationale for developing recommendations for the current Shuttle or for future programs is presented

Advanced information processing system: The Army fault tolerant architecture conceptual study. Volume 1: Army fault tolerant architecture overview

Digital computing systems needed for Army programs such as the Computer-Aided Low Altitude Helicopter Flight Program and the Armored Systems Modernization (ASM) vehicles may be characterized by high computational throughput and input/output bandwidth, hard real-time response, high reliability and availability, and maintainability, testability, and producibility requirements. In addition, such a system should be affordable to produce, procure, maintain, and upgrade. To address these needs, the Army Fault Tolerant Architecture (AFTA) is being designed and constructed under a three-year program comprised of a conceptual study, detailed design and fabrication, and demonstration and validation phases. Described here are the results of the conceptual study phase of the AFTA development. Given here is an introduction to the AFTA program, its objectives, and key elements of its technical approach. A format is designed for representing mission requirements in a manner suitable for first order AFTA sizing and analysis, followed by a discussion of the current state of mission requirements acquisition for the targeted Army missions. An overview is given of AFTA's architectural theory of operation

Multiport VNA Measurements

This article presents some of the most recent multiport VNA measurement methodologies used to characterize these highspeed digital networks for signal integrity. There will be a discussion of the trends and measurement challenges of high-speed digital systems, followed by a presentation of the multiport VNA measurement system details, calibration, and measurement techniques, as well as some examples of interconnect device measurements. The intent here is to present some general concepts and trends for multiport VNA measurements as applied to computer system board-level interconnect structures, and not to promote any particular brand or produc

Retention and application of Skylab experiences to future programs

The problems encountered and special techniques and procedures developed on the Skylab program are described along with the experiences and practical benefits obtained for dissemination and use on future programs. Three major topics are discussed: electrical problems, mechanical problems, and special techniques. Special techniques and procedures are identified that were either developed or refined during the Skylab program. These techniques and procedures came from all manufacturing and test phases of the Skylab program and include both flight and GSE items from component level to sophisticated spaceflight systems

Design and Development of an Integrated Automation Simulation System

An efficient simulation process comprises of an essential set of technological tools and approaches for the successful implementation of optimized manufacturing since it allows the makers for the trialing and validation of product, process, system design, and configuration. It also strives to engage the user completely within an experimental context, thereby greatly enhancing the overall impact through efficient use of time, workforce, and a thoroughly saved cost. Just as science further develop tools to rapidly progress the quality of commercial products, the technology transfer on the development of manufacturing systems also advances thereby creating an equal opportunity and need for different specialists to maintain these systems. These specialist are the engineers that come from the various sectors of academe and industry in which there is a great need for expertise synchronization to achieve balance in the technology acceptance.  This paper gives an highlight of the different applications of testing, drilling, clamping, and ejecting process in manufacturing industries and proposes an efficient design of a digital automation simulation system that emulates the engineering control techniques in operating a testing, drilling, clamping, and ejecting process thereby serves as an instrument for the development of 21st century learning and automation technology adaptation

Developing a Methodology to Detect Partial Failures for Dynamic Systems

The purpose of this research is to develop a decision support system that can assist in detecting partial failures in dynamic systems such as Fire Control System Tracking Radar (TR) onboard Naval Ships. Partial failures do not necessarily shut down the system immediately but cause degradation of operational performance. Previous work has shown that experts in the field of failure detection, test point insertion and Built-In-Test Equipment (BITE) can provide useful input in detecting partial failures. Partial failures affect operational system performance and support costs, which can be significant. Often, however, partial failure detection consists of the estimations and opinions of the experts. This has not been addressed adequately in the literature. It is postulated that the approach developed in this research could be applied to maintain and monitor partial failure. The development of such a testing aid is the thrust of this research effort. Markov chains, k-out-of-n: G: system and critical path tracing techniques, among others are employed. Appropriate survey questionnaires are used for validation of the resulting test model. Application of previous test point insertion techniques are applied as a part of system comparison and assessment

In-flight maintenance study Final report

Sample system analysis, MF requirements, redesign, and packaging desig

The design, fabrication, and test of a CMOS operational amplifier

The topic of this thesis is the design, fabrication, and testing of a CMOS operational Amplifier. This Operational Amplifier was first realized as a class design project for Advanced Analog IC design. Specifications for the device performance were determined by Dr. Fuller and Edward Sayre to enable the op-amp to be incorporated into a larger more complex design. The specifications of the operational amplifier were made to enable design integration into an amplifier which would operate in the audio frequency range. The main constraints placed on the design of the op-amp were low power consumption and a relatively moderate gain