On the realization of discrete cosine transform using the distributed arithmetic

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Efficient prime factor algorithm and address generation techniques for the discrete cosine transform

2001-2002 > Academic research: refereed > Publication in refereed journalVersion of RecordPublishe

Number theoretic techniques applied to algorithms and architectures for digital signal processing

Many of the techniques for the computation of a two-dimensional convolution of a small fixed window with a picture are reviewed. It is demonstrated that Winograd's cyclic convolution and Fourier Transform Algorithms, together with Nussbaumer's two-dimensional cyclic convolution algorithms, have a common general form. Many of these algorithms use the theoretical minimum number of general multiplications. A novel implementation of these algorithms is proposed which is based upon one-bit systolic arrays. These systolic arrays are networks of identical cells with each cell sharing a common control and timing function. Each cell is only connected to its nearest neighbours. These are all attractive features for implementation using Very Large Scale Integration (VLSI). The throughput rate is only limited by the time to perform a one-bit full addition. In order to assess the usefulness to these systolic arrays a 'cost function' is developed to compare them with more conventional techniques, such as the Cooley-Tukey radix-2 Fast Fourier Transform (FFT). The cost function shows that these systolic arrays offer a good way of implementing the Discrete Fourier Transform for transforms up to about 30 points in length. The cost function is a general tool and allows comparisons to be made between different implementations of the same algorithm and between dissimilar algorithms. Finally a technique is developed for the derivation of Discrete Cosine Transform (DCT) algorithms from the Winograd Fourier Transform Algorithm. These DCT algorithms may be implemented by modified versions of the systolic arrays proposed earlier, but requiring half the number of cells

Novel formulation and realisation of discrete cosine transform using distributed arithmetic

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Wide-bandwidth high-resolution search for extraterrestrial intelligence

Research accomplished in the following areas is discussed: the antenna configuration; HEMT low-noise amplifiers; the downconverter; the Fast Fourier Transform Array; the backend array; and the backend and workstation

Orthogonality Conditions for Non-Dyadic Wavelet Analysis

The conventional dyadic multiresolution analysis constructs a succession of frequency intervals in the form of ( π  / 2  j , π  / 2  j  - 1 ); j  = 1, 2, . . . ,  n of which the bandwidths are halved repeatedly in the descent from high frequencies to low frequencies. Whereas this scheme provides an excellent framework for encoding and transmitting signals with a high degree of data compression, it is less appropriate to the purposes of statistical data analysis.       A non-dyadic mixed-radix wavelet analysis is described that allows the wave bands to be defined more flexibly than in the case of a conventional dyadic analysis. The wavelets that form the basis vectors for the wave bands are derived from the Fourier transforms of a variety of functions that specify the frequency responses of the filters corresponding to the sequences of wavelet coefficients.Wavelets, Non-dyadic analysis, Fourier analysis

Hardware Implementation of a Secured Digital Camera with Built In Watermarking and Encryption Facility

The objective is to design an efficient hardware implementation of a secure digital camera for real time digital rights management (DRM) in embedded systems incorporating watermarking and encryption. This emerging field addresses issues related to the ownership and intellectual property rights of digital content. A novel invisible watermarking algorithm is proposed which uses median of each image block to calculate the embedding factor. The performance of the proposed algorithm is compared with the earlier proposed permutation and CRT based algorithms. It is seen that the watermark is successfully embedded invisibly without distorting the image and it is more robust to common image processing techniques like JPEG compression, filtering, tampering. The robustness is measured by the different quality assessment metrics- Peak Signal to Noise Ratio (PSNR), Normalized Correlation (NC), and Tampering Assessment Function (TAF). It is simpler to implement in hardware because of its computational simplicity. Advanced Encryption Standard (AES) is applied after quantization for increased security. The corresponding hardware architectures for invisible watermarking and AES encryption are presented and synthesized for Field Programmable Gate Array(FPGA).The soft cores in the form of Hardware Description Language(HDL) are available as intellectual property cores and can be integrated with any multimedia based electronic appliance which are basically embedded systems built using System On Chip (SoC) technology

DFT algorithms for bit-serial GaAs array processor architectures

Systems and Processes Engineering Corporation (SPEC) has developed an innovative array processor architecture for computing Fourier transforms and other commonly used signal processing algorithms. This architecture is designed to extract the highest possible array performance from state-of-the-art GaAs technology. SPEC's architectural design includes a high performance RISC processor implemented in GaAs, along with a Floating Point Coprocessor and a unique Array Communications Coprocessor, also implemented in GaAs technology. Together, these data processors represent the latest in technology, both from an architectural and implementation viewpoint. SPEC has examined numerous algorithms and parallel processing architectures to determine the optimum array processor architecture. SPEC has developed an array processor architecture with integral communications ability to provide maximum node connectivity. The Array Communications Coprocessor embeds communications operations directly in the core of the processor architecture. A Floating Point Coprocessor architecture has been defined that utilizes Bit-Serial arithmetic units, operating at very high frequency, to perform floating point operations. These Bit-Serial devices reduce the device integration level and complexity to a level compatible with state-of-the-art GaAs device technology