The design of a multilevel envelope tracking amplifier based on a multiphase buck converter

Envelope Tracking (ET) and Envelope Elimination and Restoration (EER) are techniques that have gained in importance in the last decade in order to obtain highly efficient Radio Frequency Power Amplifier (RFPA) that transmits signals with high Peak to Average Power Ratio (PAPR). In this work a multilevel multiphase buck converter is presented as a solution for the envelope amplifier used in ET and EER. The presented multiphase buck converter generates multilevel voltage using “node” duty cycles and non-linear control. In this way the multilevel is implemented using only one simple power stage. However, the complexity of the multilevel converter implementation has been shifted from complicated power topologies to complicated digital control. Detailed discussion regarding the influence of the design parameters (switching frequency, output filter, time resolution of the digital control) on the performance of the proposed envelope amplifier is presented. The design of the output filter is conducted fulfilling the constraints of the envelope slew rate and minimum driver pulse that can be reproduced. In the cases when these two constraints cannot be fulfilled, they may be relieved by the modified control that is presented and experimentally validated. Finally, in order to validate the concept, a prototype has been designed and integrated with a nonlinear class F amplifier. Efficiency measurements showed that by employing EER it is possible to save up to 15% of power losses, comparing to the case when it is supplied by a constant voltage. Additionally, Adjacent Channel Power Ratio (ACPR) has been measured. The obtained results showed the value higher than 30dB for signals up to 5 MHz of bandwidth, without using predistortion technique

Correction of errors and harmonic distortion in pulse-width modulation of digital signals

Article number 153991Pulse-Width (PW) modulation is widely used in those applications where an analog or digital signal has to be encoded in the time domain as a binary stream, such as switched-mode power amplifiers in transmitters of modern telecommunication standards, high-resolution digital signal conversion using single-bit digital-to-analog converters, and many others. Due to the fact that digital signals are sampled in the time domain, the quality of the resulting PW modulated waveforms is worsened by harmonic distortion. Multilevel PW modulation has been proposed to reduce these adverse effects, but the modulated waveform is no longer binary. In this paper, the mechanisms by which harmonic distortion is produced are analyzed. As a result, the distortion terms are mathematically quantified and used to correct the errors. Note that a correction network based on a simple subtraction of the distortion terms from the PW modulated signal would produce a waveform that would no longer be binary. The proposed correction network is implemented in the digital domain and, by means of a sigma-delta modulator, preserves the binary feature of the PW modulated output.Ministerio de Ciencia, Innovación y Universidades (España) RTI201- 099189-B-C2

Analysis and design of ΣΔ Modulators for Radio Frequency Switchmode Power Amplifiers

Power amplifiers are an integral part of every basestation, macrocell, microcell and mobile phone, enabling data to be sent over the distances needed to reach the receiver’s antenna. While linear operation is needed for transmitting WCDMA and OFDM signals, linear operation of a power amplifier is characterized by low power efficiency, and contributes to unwanted power dissipation in a transmitter. Recently, a switchmode power amplifier operation was considered for reducing power losses in a RF transmitter. A linear and efficient operation of a PA can be achieved when the transmitted RF signal is ΣΔ modu- lated, and subsequently amplified by a nonlinear device. Although in theory this approach offers linearity and efficiency reaching 100%, the use of ΣΔ modulation for transmitting wideband signals causes problems in practical implementation: it requires high sampling rate by the digital hardware, which is needed for shaping large contents of a quantization noise induced by the modulator but also, the binary output from the modulator needs an RF power amplifier operating over very wide frequency band. This thesis addresses the problem of noise shaping in a ΣΔ modulator and nonlinear distortion caused by broadband operation in switchmode power amplifier driven by a ΣΔ modulated waveform. The problem of sampling rate increase in a ΣΔ modulator is solved by optimizing structure of the modulator, and subsequent processing of an input signal’s samples in parallel. Independent from the above, a novel technique for reducing quan- tization noise in a bandpass ΣΔ modulator using single bit quantizer is presented. The technique combines error pulse shaping and 3-level quantization for improving signal to noise ratio in a 2-level output. The improvement is achieved without the increase of a digital hardware’s sampling rate, which is advantageous also from the perspective of power consumption. The new method is explored in the course of analysis, and verified by simulated and experimental results. The process of RF signal conversion from the Cartesian to polar form is analyzed, and a signal modulator for a polar transmitter with a ΣΔ-digitized envelope signal is designed and implemented. The new modulator takes an advantage of bandpass digital to analog conversion for simplifying the analog part of the modulator. A deformation of the pulsed RF signal in the experimental modulator is demonstrated to have an effect primarily on amplitude of the RF signal, which is correctable with simple predistortion

Class-D Audio Amplifier using Sigma-Delta (ΣΔ) Modulator

Pulse width modulation and pulse density modulation are deemed to be main modulation techniques, even PDM could not emulate PWM, in terms of, basically, simplicity. PDM bitstream is encoded through sigma-delta modulation. Since sigma-delta modulation, compared to PWM, needs very high switching frequency and more complicated materials to compose circuits, it’s more difficult to design one. In this article we design a low-power class-D audio amplifier circuit where the analog signal is encoded into pulse density modulation (PDM) using a first-order sigma-delta (ΣΔ) modulator. The designed circuit is built using Orcad-PSpice and results are analyzed with Matlab. A second-order integrator, a voltage divider as a feedback loop are used to mitigate basically, THD and get high efficiency. The audio signal is passed to the EM speaker through a Butterworth low-pass filter. A low THD of less than 0.2 % is obtained comparing to similar circuits in the literature and a high efficiency of 92 % is achieved.

mmWave Spatial-Temporal Single Harmonic Switching Transmitter Arrays for High back-off Beamforming Efficiency

This paper presents a spatial-temporal single harmonic switching (STHS) transmitter array architecture with enhanced efficiency in the power back-off (PBO) region. STHS is an electromagnetic and circuit co-designed and jointly optimized transmitter array that realizes beamforming and back-off power generation at the same time. The temporal dimension is originally added in STHS to achieve back-off efficiency enhancement, which can be combined with conventional power back-off enhancement methods such as Doherty amplifiers and envelope tracking. The design is validated through a simulation of a two-stage power amplifier in 65-nm CMOS at 77 GHz, which achieves a peak drain efficiency (DE) of 24.2%, a 22% DE at 3-dB PBO, 16% DE at 6-dB PBO, and 10.2% at 9-dB PBO. The efficiency exhibits a 57% improvement at 3-dB PBO, 100% improvement at 6-dB PBO, and 190% improvement at 9-dB PBO compared with class A/B amplifier

Linearized 9-Bit Hybrid LBDD PWM Modulator for Digital Class-BD Amplifier

The paper presents an original architecture andimplementation of 9-bit Linearized Pulse Width Modulator(LPWM) for Class-BD amplifier, based on the hybrid methodusing STM32 microcontroller and Programmable Tapped DelayLine (PTDL). The analog input signals are converted into 12-bitPCM signals, then are directly transformed into 32-bit LBDDDPWM data of the pulse-edge locations within n-th period of theswitching frequency, next requantized to the 9-bit digitaloutputs, and finally converted into the two physical trains of 1-bitPWM signals, to control the output stage of the Class-BD audioamplifier. The hybrid 9-bit quantizer converts 6 MSB bits usingcounter method, based on the peripherals of STM32microcontroller, while the remaining 3 LSB bits - using a methodbased on the PTDL. In the paper extensive verification ofalgorithm and circuit operation as well as simulation inMATLAB and experimental results of the proposed 9-bit hybridLBDD DPWM circuit have been performed. It allows to attainSNR of 80 dB and THD about 0,3% within the audio baseband

Linearized 9-Bit Hybrid LBDD PWM Modulator for Digital Class-BD Amplifier

The paper presents an original architecture andimplementation of 9-bit Linearized Pulse Width Modulator(LPWM) for Class-BD amplifier, based on the hybrid methodusing STM32 microcontroller and Programmable Tapped DelayLine (PTDL). The analog input signals are converted into 12-bitPCM signals, then are directly transformed into 32-bit LBDDDPWM data of the pulse-edge locations within n-th period of theswitching frequency, next requantized to the 9-bit digitaloutputs, and finally converted into the two physical trains of 1-bitPWM signals, to control the output stage of the Class-BD audioamplifier. The hybrid 9-bit quantizer converts 6 MSB bits usingcounter method, based on the peripherals of STM32microcontroller, while the remaining 3 LSB bits - using a methodbased on the PTDL. In the paper extensive verification ofalgorithm and circuit operation as well as simulation inMATLAB and experimental results of the proposed 9-bit hybridLBDD DPWM circuit have been performed. It allows to attainSNR of 80 dB and THD about 0,3% within the audio baseband