Efficient Universal Computing Architectures for Decoding Neural Activity

The ability to decode neural activity into meaningful control signals for prosthetic devices is critical to the development of clinically useful brain– machine interfaces (BMIs). Such systems require input from tens to hundreds of brain-implanted recording electrodes in order to deliver robust and accurate performance; in serving that primary function they should also minimize power dissipation in order to avoid damaging neural tissue; and they should transmit data wirelessly in order to minimize the risk of infection associated with chronic, transcutaneous implants. Electronic architectures for brain– machine interfaces must therefore minimize size and power consumption, while maximizing the ability to compress data to be transmitted over limited-bandwidth wireless channels. Here we present a system of extremely low computational complexity, designed for real-time decoding of neural signals, and suited for highly scalable implantable systems. Our programmable architecture is an explicit implementation of a universal computing machine emulating the dynamics of a network of integrate-and-fire neurons; it requires no arithmetic operations except for counting, and decodes neural signals using only computationally inexpensive logic operations. The simplicity of this architecture does not compromise its ability to compress raw neural data by factors greater than . We describe a set of decoding algorithms based on this computational architecture, one designed to operate within an implanted system, minimizing its power consumption and data transmission bandwidth; and a complementary set of algorithms for learning, programming the decoder, and postprocessing the decoded output, designed to operate in an external, nonimplanted unit. The implementation of the implantable portion is estimated to require fewer than 5000 operations per second. A proof-of-concept, 32-channel field-programmable gate array (FPGA) implementation of this portion is consequently energy efficient. We validate the performance of our overall system by decoding electrophysiologic data from a behaving rodent.United States. National Institutes of Health (Grant NS056140

Neuromorphic-Based Neuroprostheses for Brain Rewiring: State-of-the-Art and Perspectives in Neuroengineering.

Neuroprostheses are neuroengineering devices that have an interface with the nervous system and supplement or substitute functionality in people with disabilities. In the collective imagination, neuroprostheses are mostly used to restore sensory or motor capabilities, but in recent years, new devices directly acting at the brain level have been proposed. In order to design the next-generation of neuroprosthetic devices for brain repair, we foresee the increasing exploitation of closed-loop systems enabled with neuromorphic elements due to their intrinsic energy efficiency, their capability to perform real-time data processing, and of mimicking neurobiological computation for an improved synergy between the technological and biological counterparts. In this manuscript, after providing definitions of key concepts, we reviewed the first exploitation of a real-time hardware neuromorphic prosthesis to restore the bidirectional communication between two neuronal populations in vitro. Starting from that 'case-study', we provide perspectives on the technological improvements for real-time interfacing and processing of neural signals and their potential usage for novel in vitro and in vivo experimental designs. The development of innovative neuroprosthetics for translational purposes is also presented and discussed. In our understanding, the pursuit of neuromorphic-based closed-loop neuroprostheses may spur the development of novel powerful technologies, such as 'brain-prostheses', capable of rewiring and/or substituting the injured nervous system

A Cognitive Approach to Mobile Robot Environment Mapping and Path Planning

This thesis presents a novel neurophysiological based navigation system which uses less memory and power than other neurophysiological based systems, as well as traditional navigation systems performing similar tasks. This is accomplished by emulating the rodent’s specialized navigation and spatial awareness brain cells, as found in and around the hippocampus and entorhinal cortex, at a higher level of abstraction than previously used neural representations. Specifically, the focus of this research will be on replicating place cells, boundary cells, head direction cells, and grid cells using data structures and logic driven by each cell’s interpreted behavior. This method is used along with a unique multimodal source model for place cell activation to create a cognitive map. Path planning is performed by using a combination of Euclidean distance path checking, goal memory, and the A* algorithm. Localization is accomplished using simple, low power sensors, such as a camera, ultrasonic sensors, motor encoders and a gyroscope. The place code data structures are initialized as the mobile robot finds goal locations and other unique locations, and are then linked as paths between goal locations, as goals are found during exploration. The place code creates a hybrid cognitive map of metric and topological data. In doing so, much less memory is needed to represent the robot’s roaming environment, as compared to traditional mapping methods, such as occupancy grids. A comparison of the memory and processing savings are presented, as well as to the functional similarities of our design to the rodent’ specialized navigation cells

NEUROMORPHIC VLSI REALIZATION OF THE HIPPOCAMPAL FORMATION AND THE LATERAL SUPERIOR OLIVE

In this work, the focus is on realizing the function of the hippocampal formation (HF) and the lateral superior olive (LSO) in electronic circuits. The first major contribution of this dissertation is to realize the function of the HF in silicon. This was based on the GRIDSmap model and the Bayesian integration. For this, two novel circuits were designed and integrated with others. The first circuit was that of a Bayesian integration synapse which can perform Bayesian integration at the single neuron level. The second circuit was that of a velocity integrator which is so compact that it can enable integration of the entire system on a single chip compared to its predecessors which would have needed 27 chips! However, since the computational neuroscience models of the hippocampal place cells do not explain all the characteristics observed empirically, a novel model for the place cells, based on the sensori-motor integration of inputs is proposed. This is the second major contribution of this thesis. The third major contribution is to demonstrate a VLSI system which can perform azimuthal localization based on population response of the LSO. This system was based on the Reed and Blum's model of the LSO. For this, a novel circuit of a second order synapse and that of a conductance neuron was designed and integrated with other circuits. This synapse circuit can produce an output current whose peak is delayed and is proportional to the number of inputs it receives. The HF is thought to aid in spatial navigation and the LSO is thought to be involved in azimuthal localization of sounds both of which are useful for autonomous robotic spatial navigation. Hence, silicon realization of these two will be useful in robotics which is an area of interest for the neuromorphic engineers

Closed-loop approaches for innovative neuroprostheses

The goal of this thesis is to study new ways to interact with the nervous system in case of damage or pathology. In particular, I focused my effort towards the development of innovative, closed-loop stimulation protocols in various scenarios: in vitro, ex vivo, in vivo

Scalable Digital Architecture of a Liquid State Machine

Liquid State Machine (LSM) is an adaptive neural computational model with rich dynamics to process spatio-temporal inputs. These machines are extremely fast in learning because the goal-oriented training is moved to the output layer, unlike conventional recurrent neural networks. The capability to multiplex at the output layer for multiple tasks makes LSM a powerful intelligent engine. These properties are desirable in several machine learning applications such as speech recognition, anomaly detection, user identification etc. Scalable hardware architectures for spatio-temporal signal processing algorithms like LSMs are energy efficient compared to the software implementations. These designs can also naturally adapt to dierent temporal streams of inputs. Early literature shows few behavioral models of LSM. However, they cannot process real time data either due to their hardware complexity or xed design approach. In this thesis, a scalable digital architecture of an LSM is proposed. A key feature of the architecture is a digital liquid that exploits spatial locality and is capable of processing real time data. The quality of the proposed LSM is analyzed using kernel quality, separation property of the liquid and Lyapunov exponent. When realized using TSMC 65nm technology node, the total power dissipation of the liquid layer, with 60 neurons, is 55.7 mW with an area requirement of 2 mm^2. The proposed model is validated for two benchmark. In the case of an epileptic seizure detection an average accuracy of 84% is observed. For user identification/authentication using gait an average accuracy of 98.65% is achieved

Autonomously Reconfigurable Artificial Neural Network on a Chip

Artificial neural network (ANN), an established bio-inspired computing paradigm, has proved very effective in a variety of real-world problems and particularly useful for various emerging biomedical applications using specialized ANN hardware. Unfortunately, these ANN-based systems are increasingly vulnerable to both transient and permanent faults due to unrelenting advances in CMOS technology scaling, which sometimes can be catastrophic. The considerable resource and energy consumption and the lack of dynamic adaptability make conventional fault-tolerant techniques unsuitable for future portable medical solutions. Inspired by the self-healing and self-recovery mechanisms of human nervous system, this research seeks to address reliability issues of ANN-based hardware by proposing an Autonomously Reconfigurable Artificial Neural Network (ARANN) architectural framework. Leveraging the homogeneous structural characteristics of neural networks, ARANN is capable of adapting its structures and operations, both algorithmically and microarchitecturally, to react to unexpected neuron failures. Specifically, we propose three key techniques --- Distributed ANN, Decoupled Virtual-to-Physical Neuron Mapping, and Dual-Layer Synchronization --- to achieve cost-effective structural adaptation and ensure accurate system recovery. Moreover, an ARANN-enabled self-optimizing workflow is presented to adaptively explore a "Pareto-optimal" neural network structure for a given application, on the fly. Implemented and demonstrated on a Virtex-5 FPGA, ARANN can cover and adapt 93% chip area (neurons) with less than 1% chip overhead and O(n) reconfiguration latency. A detailed performance analysis has been completed based on various recovery scenarios