Design of a dual OPAMP low offset integrator system for plasma reactor

In a fusion reactor, where tokamaks are used to confine the plasma using toroidal and poloidal magnetic fields, highly accurate magnetic measurements are a necessity for automatic control. However, due to extremities in temperature, acquiring uncorrupted signals become a challenging task. Presented in this thesis is a design of a twin operational amplifier based low offset integrating system to eliminate any error in measurement due to temperature dependent DC offset. This integrator system comprises mainly three stages after the inductive sensor. The first stage consists of a dual integrator in which the output signal from the sensor was fed to one integrator and the input terminals of the other integrator were grounded. An instrumentation amplifier which has a very high common mode rejection ratio and large input impedance was implemented in the second stage to find the differential signal between the outputs of the two integrators. Any noise arising in the environment was eliminated in the next stage by a Digital Signal Processor based Finite Impulse Response Low-Pass Filter. The first two stages of the design were simulated by using Multisim Circuit Design Suite. The low-pass filtering stage was realized on a Texas Instruments TMS320C6713 starter kit using Kaiser Windowing technique to achieve a sharp cut-off at 780Hz. To obtain a full layout of the operational amplifier based design Cadence Electronic Design Automation UMC_180 nm tool was used. The primary objective of DC offset elimination was verified through the results. KEY WORDS: Inductive Sensor, Operational Amplifier, Integrator, Instrumentation Amplifier, Low-pass Filte

Parallel Quantum Computing Emulation

Quantum computers provide a fundamentally new computing paradigm that promises to revolutionize our ability to solve broad classes of problems. Surprisingly, the basic mathematical structures of gate-based quantum computing, such as unitary operations on a finite-dimensional Hilbert space, are not unique to quantum systems but may be found in certain classical systems as well. Previously, it has been shown that one can represent an arbitrary multi-qubit quantum state in terms of classical analog signals using nested quadrature amplitude modulated signals. Furthermore, using digitally controlled analog electronics one may manipulate these signals to perform quantum gate operations and thereby execute quantum algorithms. The computational capacity of a single signal is, however, limited by the required bandwidth, which scales exponentially with the number of qubits when represented using frequency-based encoding. To overcome this limitation, we introduce a method to extend this approach to multiple parallel signals. Doing so allows a larger quantum state to be emulated with the same gate time required for processing frequency-encoded signals. In the proposed representation, each doubling of the number of signals corresponds to an additional qubit in the spatial domain. Single quit gate operations are similarly extended so as to operate on qubits represented using either frequency-based or spatial encoding schemes. Furthermore, we describe a method to perform gate operations between pairs of qubits represented using frequency or spatial encoding or between frequency-based and spatially encoded qubits. Finally, we describe how this approach may be extended to represent qubits in the time domain as well.Comment: 9 pages, 4 figures, 2018 IEEE International Conference on Rebooting Computing (ICRC

A charge-metering method for voltage-mode neural stimulation

AbstractElectrical neural stimulation is the technique used to modulate neural activity by inducing an instantaneous charge imbalance. This is typically achieved by injecting a constant current and controlling the stimulation time. However, constant voltage stimulation is found to be more energy-efficient although it is challenging to control the amount of charge delivered. This paper presents a novel, fully integrated circuit for facilitating charge-metering in constant voltage stimulation. It utilises two complementary stimulation paths. Each path includes a small capacitor, a comparator and a counter. They form a mixed-signal integrator that integrates the stimulation current onto the capacitor while monitoring its voltage against a threshold using the comparator. The pulses from the comparator are used to increment the counter and reset the capacitor. Therefore, by knowing the value of the capacitor, threshold voltage and output of the counter, the quantity of charge delivered can be calculated. The system has been fabricated in 0.18μm CMOS technology, occupying a total active area of 339μm×110μm. Experimental results were taken using: (1) a resistor–capacitor EEI model and (2) platinum electrodes with ringer solution. The viability of this method in recruiting action potentials has been demonstrated using a cuff electrode with Xenopus sciatic nerve. For a 10nC target charge delivery, the results of (2) show a charge delivery error of 3.4% and a typical residual charge of 77.19pC without passive charge recycling. The total power consumption is 45μW. The performance is comparable with other publications. Therefore, the proposed stimulation method can be used as a new approach for neural stimulation