A Methodology to Design FPGA-based PID Controllers

This paper presents a methodology to implement PID (Proportional, Integral, Derivative) controllers in FPGAs (Field-Programmable Gate Arrays) using fixed-point numerical representation. The Matlab/Simulink environment is used for modeling, simulation and evaluation the performance provided by different fixed-point representations using a given control process. A static bit-width analyzer is used to give a specialized fixed-point representation for each operand/operator in the controller system. After bit-width analysis, a VHDL represen-tation of the system is generated. Results show that the proposed methodology leads to shorten design cycles achieving important resource savings by employing specialized fixed-point repre-sentations

Neuronal imaging with ultrahigh dynamic range multiphoton microscopy

Multiphoton microscopes are hampered by limited dynamic range, preventing weak sample features from being detected in the presence of strong features, or preventing the capture of unpredictable bursts in sample strength. We present a digital electronic add-on technique that vastly improves the dynamic range of a multiphoton microscope while limiting potential photodamage. The add-on provides real-time negative feedback to regulate the laser power delivered to the sample, and a log representation of the sample strength to accommodate ultrahigh dynamic range without loss of information. No microscope hardware modifications are required, making the technique readily compatible with commercial instruments. Benefits are shown in both structural and in-vivo functional mouse brain imaging applications.R21 EY027549 - NEI NIH HH

Power Efficient MAC Unit Based Digital PID Controllers

Proper closed loop has been an ever hot issue in the automotive industry. The industrial equipments governed by PID controllers have very simple control architecture and efficiency but still they find a trouble dueto large power consumption and slow mathematical computation. Many researchers have worked out and are trying to design a low power, less delay PID. This paper reviews three MAC architectures with array, booth and wallace tree multipliers incorporated in PID architecture. The simulations are done and the area, power, delay results are synthesized using Xilinx ISE. Comparisons are made between these three architectures in terms of power delay product and area delay product

Design and Implementation of FPGA based linear All Digital Phase-Locked Loop for Signal Processing Applications

This project presents a linear all-digital phase locked loop based on FPGA. In this ADPLL the phase detection system is realized by generating an analytic signal using a compact implementation of Hilbert transform and then simply computing the instantaneous phase using CORDIC algorithm in vectoring mode of operation. A 16-bit pipelined CORDIC algorithm is employed in order to obtain the phase information of the signal. All the components used in this phase detection system are realized as digital discrete time components. This design does not involve any class of multipliers thus reducing the complexity of the design. The loop filter of the ADPLL has been designed using PI controller which has a low pass behavior and is used to discard the higher order harmonics of the error signal. The CORDIC algorithm in its rotation mode of operation is used to compute sinusoidal values for the DDS. The ADPLL model has been implemented using Xilinx ISE 12.3 and ModelSim PE Student Edition 10.1a. The ADPLL model describes a novel method of implementation of CORDIC algorithm for the DDS system. This ADPLL model basically used for synchronization of closed loop RF control signals in a heavy ion particle accelerator can be implemented even in an ASIC which can be seen with a more general use for many a applications in the daily life

Design of high-speed and low-power finite-word-length PID controllers.

International audienceASIC or FPGA implementation of a finite word-length PID controller requires a double expertise : in control system and hardware design. In this paper, we only focus on the hardware side of the problem. We show how to design configurable fixed-point PIDs to satisfy application srequiring minimal power consumption, or high control-rate, or both together. As multiply operation is the engine of PID, we experienced three algorithms : Booth, modified Booth, and a new recursive multi-bit multiplication algorithm. This later enables the construction of finely grained PID structures with bit-velvel and unit-time precsion. Such a feature permits to tailor the PID to the desired performance and power budget. All PIDs are emplemented at register-transfer-level (RTL) level as technology-independent reusable IP-cores. They are reconfigurable according to two compile-time constants : set-point word-length and latency. To make PID design easily reproducible, all necessary implementation details are provided and discussed

Enriching MATLAB with aspect-oriented features for developing embedded systems

This article presents an approach to enrich the MATLAB language with aspect-oriented modularity features, enabling developers to experiment different implementation characteristics and to acquire runtime data and traces without polluting their base MATLAB code. We propose a language through which programmers configure the low-level data representation of variables and expressions. Examples include specifically-tailored fixed-point data representations leading to more efficient support for the underlying hardware, e.g., digital signal processors and application-specific architectures, without built-in floating point units. This approach assists developers in adding handlers and monitoring features in a non-invasive way as well as configuring MATLAB functions with optimized implementations. Different aspect modules can be used to retarget common MATLAB code bases for different purposes and implementations. We validate the proposed approach with a set of representative examples where we attain a simple way to explore a number of properties. Experiment results and collected aspect-oriented software metrics lend support to the claims on its usefulness.This work was partially supported by FCT (Portuguese Science Foundation) under the project AMADEUS (POCTI, PTDC/EIA/70271/2006)

PID-säätimen optimointi differentiaalievoluutiolla

Differentiaalievoluutio on uusi optimointimenetelmä, joka soveltuu erinomaisesti PID-säätimen parametrien numeeriseen optimointiin yksinkertaisuutensa ja reaaliaikaisuutensa vuoksi. Tässä tutkimuksessa PID-säädintä optimoidaan FPGA:lla. FPGA:lla ei ole aiemmin toteutettu tällaista differentiaalievoluutiomene-telmään perustuvaa PID-säädintä. Alkuperäistä differentiaalievoluutioalgoritmia parannetaan ranking-perusteisella mutaatio-operaatiolla ja itse-adaptoituvilla mutaatio- ja risteytysparametreilla. Ranking-perusteisella mutaatio-operaatiolla pystytään parantamaan ratkaisun optimoinnin onnistumis-todennäköisyyttä, laatua ja suppenemisnopeutta. Lisäksi itse-adaptoituvien ohjausparametrien ansiosta käyttäjän ei tarvitse arvioida mutaatio- ja risteytys-parametrien arvoja. FPGA:lla optimoidaan kustannusfunktiota, joka koostuu eroarvosta, näytteenottovälistä ja derivointi-termistä. Hyvyysarvo lasketaan yritevektorin paramet-reista sukupolvittain. Hyvyyslaskennan perusteella valitaan parhaat yriteparametrit optimiparametreiksi. PID-säädinohjelma on ensin testattu Modelsimilla ja tämän jälkeen kyseiset testaustulokset on analysoitu Matlabilla. Tulosten perusteella ohjelman eri osa-alueita voidaan tulevaisuudessa kehittää sekä laajentamalla ja monimutkaistamalla satunnaisuutta että kasvattamalla yksilöiden ja sukupolvien määrää. Edellä mainituilla toimenpiteillä vaikutettaisiin satunnaislukujen määrään ja toistuvuuteen ja lisättäisiin mutaatiolaskennan monimuotoisuutta.fi=Opinnäytetyö kokotekstinä PDF-muodossa.|en=Thesis fulltext in PDF format.|sv=Lärdomsprov tillgängligt som fulltext i PDF-format