Circuitos digitais em modo de corrente

Mestrado em Engenharia Electrónica e TelecomunicaçõesEste trabalho de dissertação insere-se na área da electrónica digital, e consiste no projecto, construção e caracterização de circuitos digitais em Modo de Corrente, empregando estratégias de desenho MCML (MOS Current Mode Logic). Circuitos MCML apresentam como principais vantagens um bom compromisso entre o analógico e digital e potência dissipada constante, sendo desta forma uma boa solução para aplicações que exigem altas velocidades de operação. Neste trabalho são abordadas as principais características da lógica MCML relativas ao projecto de circuitos digitais através de uma análise detalhada do inversor MCML. É ainda efectuada uma abordagem sobre as metodologias para implementação/desenho das principais funções lógicas, bem como uma análise comparativa das suas características. Posteriormente implementa-se um conjunto de portas lógicas, analisando as diferentes topologias provenientes do método de implementação adoptado. Para analisar o desempenho de circuitos MCML, projectou-se algumas funções lógicas, em tecnologia CMOS 350nm da AMS, procedendo à sua simulação e caracterização.The present dissertation is inserted in the general subject of digital electronics, and discusses the design, layout and characterization of current-mode digital circuits using MCML design strategies. MCML circuits exhibit major advantages in digital design, like a constant power consumption, and present a good compromise for analog and digital applications. This work addresses the most important characteristics of MCML logic for the design of digital circuitry through a detailed analysis of the MCML inverter. The basic methodologies used for implementation/layout of the most important logical functions are assessed, and a comparative analysis of their characteristics is performed. Further on, the set of logic gates designed in the course of this work is presented, allowing for the analysis of different topologies from the chosen implementation methodology. Finally, in order to analyze the performance of MCML circuits, several logic functions where implemented using the AMS 350nm CMOS technology. The respective characterization and simulation results are presented and discussed

CMOS design of adaptive fuzzy ASICs using mixed-signal circuits

Analog circuits are natural candidates to design fuzzy chips with optimum speed/power figures for precision up to about 1%. This paper presents a methodology and circuit blocks to realize fuzzy controllers in the form of analog CMOS chips. These chips can be made to adapt their function through electrical control. The proposed design methodology emphasizes modularity and simplicity at the circuit level - prerequisites to increasing processor complexity and operation speed. The paper include measurements from a silicon prototype of a fuzzy controller chip in CMOS 1.5 /spl mu/m single-poly technology

Using Building Blocks to Design Analog Neuro-Fuzzy Controllers

We present a parallel architecture for fuzzy controllers and a methodology for their realization as analog CMOS chips for low- and medium-precision applications. These chips can be made to learn through the adaptation of electrically controllable parameters guided by a dedicated hardware-compatible learning algorithm. Our designs emphasize simplicity at the circuit level—a prerequisite for increasing processor complexity and operation speed. Examples include a three-input, four-rule controller chip in 1.5-μm CMOS, single-poly, double-metal technology

Modular Design of Adaptive Analog CMOS Fuzzy Controller Chips

Analog circuits are natural candidates to design fuzzy chips with optimum speed/power figures for precision up to about 1%. This paper presents a methodology and circuit blocks to realize fuzzy controllers in the form of analog CMOS chips. These chips can be made to adapt their function through electrical control. The proposed design methodology emphasizes modularity and simplicity at the circuit level -- prerequisites to increasing processor complexity and operation speed. The paper include measurements from a silicon prototype of a fuzzy controller chip in CMOS 1.5μm single-poly technology

Radiation Risks and Mitigation in Electronic Systems

Electrical and electronic systems can be disturbed by radiation-induced effects. In some cases, radiation-induced effects are of a low probability and can be ignored; however, radiation effects must be considered when designing systems that have a high mean time to failure requirement, an impact on protection, and/or higher exposure to radiation. High-energy physics power systems suffer from a combination of these effects: a high mean time to failure is required, failure can impact on protection, and the proximity of systems to accelerators increases the likelihood of radiation-induced events. This paper presents the principal radiation-induced effects, and radiation environments typical to high-energy physics. It outlines a procedure for designing and validating radiation-tolerant systems using commercial off-the-shelf components. The paper ends with a worked example of radiation-tolerant power converter controls that are being developed for the Large Hadron Collider and High Luminosity-Large Hadron Collider at CERN.Comment: 19 pages, contribution to the 2014 CAS - CERN Accelerator School: Power Converters, Baden, Switzerland, 7-14 May 201

Current-mode piecewise-linear function generators

We present a systematic design technique for current-mode piecewise-linear (PWL) function generators. It uses two building blocks: a high-resolution current rectifier, and a programmable current amplifier. We show how to arrange these blocks to obtain basic non-linearities from which generic characteristics are built through aggregations. Measurements from a 1.0 /spl mu/m CMOS prototype chip show 10 pA resolution in the rectification operation and 0.6% non-linearity errors in the programmable scaling operation for 2 /spl mu/A input current range

The Rolf of Test Chips in Coordinating Logic and Circuit Design and Layout Aids for VLSI

This paper emphasizes the need for multipurpose test chips and comprehensive procedures for use in supplying accurate input data to both logic and circuit simulators and chip layout aids. It is shown that the location of test structures within test chips is critical in obtaining representative data, because geometrical distortions introduced during the photomasking process can lead to significant intrachip parameter variations. In order to transfer test chip designs quickly, accurately, and economically, a commonly accepted portable chip layout notation and commonly accepted parametric tester language are needed. In order to measure test chips more accurately and more rapidly, parametric testers with improved architecture need to be developed in conjunction with innovative test structures with on-chip signal conditioning

Integrated chaos generators

This paper surveys the different design issues, from mathematical model to silicon, involved on the design of integrated circuits for the generation of chaotic behavior.Comisión Interministerial de Ciencia y Tecnología 1FD97-1611(TIC)European Commission ESPRIT 3110