Jig mata alat bagi kerja melarik bulat

Kerja melarik bulat merupakan kerja yang biasa dilakukan menggunakan mesin larik. Projek telah diinovasikan daripada permasalahan yang timbul dalam proses melarik bulat dengan menggunakan mesin larik konvensional sebelum ini. Bertitik tolak dari permasalahan tersebut, satu kajian dan perbincangan telah dijalankan bagi mencari penyelesaian kepada masalah tersebut. Jig mata alat melarik bulat ialah suatu projek hasil cetusan idea untuk penambahbaikan bagi menggantikan sistem lama yang menggunakan teknik menggerakkan paksi X dan Y. Ianya direka khas untuk memudahkan proses melarik bulat pada mesin larik konvensional. Dengan menggunakan jig mata alat bagi kerja melarik bulat ini proses kerja di mesin menjadi lebih singkat dan menjimatkan masa serta produk yang dihasilkan lebih bermutu. Bagi industri yang mementingkan produktiviti dan keselamatan operator semasa menjalankan proses pemesinan, jig mata alat bagi kerja melarik bulat direka bagi memastikan keselamatan pengguna terjamin. Kajian ini telah diuji keboleh fungsiannya serta beberapa aspek daripada 3 orang pakar bidang yang mempunyai kelayakan akedamik dan kemahiran yang diperakui. Purata nilai min sebanyak 3.7 menunjukkan skor analisis adalah tinggi. Pakar bidang bersetuju bahawa produk ini berfungsi dengan baik. Dengan ini produk ini telah berjaya dilaksanakan

Proceedings of the Doctoral Consortium in Computer Science (JIPII 2021)

Actas de las Jornadas de Investigación Predoctoral en Ingeniería InformáticaThis volume contains the proceedings of the Primeras Jornadas de Investigación Predoctoral en Ingeniería Informática - First Doctoral Consortium in Computer Science, JIPII 2021, which was held online on June 15th, 2021. The aim of JIPII 2021 was to provide a forum for PhD students to present and discuss their research under the guidance of a panel of senior researchers. The advances in their PhD theses under development in the Doctoral Program in Computer Science were presented in the Consortium. This Doctoral Program belongs to the Doctoral School of the University of Cadiz (EDUCA). Different stages of research were covered, from the most incipient phase, such as the PhD Thesis plans (or even a Master’s Thesis), to the most advanced phases in which the defence of the PhD Thesis is imminent. We enjoyed twenty very nice and interesting talks, organized in four sessions. We had a total of fifty participants, including speakers and attendees, with an average of thirty-two people in the morning sessions and an average of twenty people in the afternoon sessions. Several people contributed to the success of JIPII 2021. We are grateful to the Academic Committee of the Doctoral Program in Computer Science and the School of Engineering for their support. We would like also to thank the Program Committee for their work in reviewing the papers, as well as all the students and supervisors for their interest and participation. Finally, the proceedings have been published by the Department of Computer Science and Engineering. We hope that you find the proceedings useful, interesting, and challenging

On the automated compilation of UML notation to a VLIW chip multiprocessor

With the availability of more and more cores within architectures the process of extracting implicit and explicit parallelism in applications to fully utilise these cores is becoming complex. Implicit parallelism extraction is performed through the inclusion of intelligent software and hardware sections of tool chains although these reach their theoretical limit rather quickly. Due to this the concept of a method of allowing explicit parallelism to be performed as fast a possible has been investigated. This method enables application developers to perform creation and synchronisation of parallel sections of an application at a finer-grained level than previously possible, resulting in smaller sections of code being executed in parallel while still reducing overall execution time. Alongside explicit parallelism, a concept of high level design of applications destined for multicore systems was also investigated. As systems are getting larger it is becoming more difficult to design and track the full life-cycle of development. One method used to ease this process is to use a graphical design process to visualise the high level designs of such systems. One drawback in graphical design is the explicit nature in which systems are required to be generated, this was investigated, and using concepts already in use in text based programming languages, the generation of platform-independent models which are able to be specialised to multiple hardware architectures was developed. The explicit parallelism was performed using hardware elements to perform thread management, this resulted in speed ups of over 13 times when compared to threading libraries executed in software on commercially available processors. This allowed applications with large data dependent sections to be parallelised in small sections within the code resulting in a decrease of overall execution time. The modelling concepts resulted in the saving of between 40-50% of the time and effort required to generate platform-specific models while only incurring an overhead of up to 15% the execution cycles of these models designed for specific architectures

A Methodology for UML Models V&V

The introduction of UML models in the software life cycle poses new issues and challenges that are not adequately supported by current state-of-the-art development tools, especially concerning V&V activities. Indeed, every tool usually focuses on a small set of specialized activities, failing to provide a satisfactory (general purpose) V&V framework. In this paper we propose a methodology which allows a seamless integration of V&V into a UML-based development environment. The methodology exploits a set of supporting tools designed to be integrated in a unified framework. We believe that such proactive collaboration between tools can reduce significantly both effort and time required to tackle consistency, correctness, quality and long-term maintainability of UML models, increasing the development productivity and the overall quality of the delivered system