844 research outputs found
CMOS/Bipolar current conveyor design and development
The aim of this research programme was to design and develop a novel CMOS
current conveyor, to improve areas such as bandwidth, slew rate, gain, and Powe-
Supply Reject Ratio (PSRR). The current conveyor can be used in low frequency
applications such as LED drivers for mobile phones and televisions, and high
frequency applications such as mixers for up/down converters used in anything from
radios to mobile phones.
The initial part of the research looked into improving the Power Supply Rejection
Ration (PSRR) of the current follower (mirror) by increasing its output impedance.
Several types of current mirror were compared using analytical and simulation
methods, using a new generic low frequency transistor model which was used to
highlight the differences in impedance between BJT and CMOS current mirrors. It
was found that the best type of mirror was the regulated cascode current mirror which
offered the largest value of output impedance when built from CMOS transistors.
Work then moved onto the voltage follower. By initially using a typical CMOS source
follower, it was found that the voltage gain suffered from low values
transconductance, drain/source resistance, and a larger than expected value of source
resistance, which was extracted from simulation and was found to be around 300-
350Q. The best design was a two stage un-buffered amplifier which offered the best
Power Supply Rejection (PSRR) voltage gain and bandwidth.
Several different types of current conveyor (CCII+) were simulated and the results
were compared. It was found that the best types of current conveyor were the cascode
type conveyors which offered a voltage gain error of less than 1%. The regulated
cascode type current conveyor offered the highest figure of PSRR that of around
60dB.
Finally the new cascode type current conveyors were used to build examples of
current feedback operational amplifiers (CFOAs), and the cascode type CCIl+ offered
a voltage gain error of less than I%, largest bandwidth and best P SRR
FVF-Based Low-Dropout Voltage Regulator with Fast Charging/Discharging Paths for Fast Line and Load Regulation
A new internally compensated low drop-out voltage
regulator based on the cascoded flipped voltage follower is
presented in this paper. Adaptive biasing current and fast
charging/discharging paths have been added to rapidly
charge and discharge the parasitic capacitance of the pass
transistor gate, thus improving the transient response. The
proposed regulator was designed with standard 65-nm
CMOS technology. Measurements show load and line
regulations of 433.80 μV/mA and 5.61 mV/V, respectively.
Furthermore, the output voltage spikes are kept under
76 mV for 0.1 mA to 100 mA load variations and 0.9 V to
1.2 V line variations with rise and fall times of 1 μs. The
total current consumption is 17.88 μA (for a 0.9 V supply
voltage).Ministerio de EconomÃa y Competitividad TEC2015-71072-C3-3-RConsejerÃa de EconomÃa, Innovación y Ciencia. Junta de AndalucÃa P12-TIC-186
Differential temperature sensors: Review of applications in the test and characterization of circuits, usage and design methodology
Differential temperature sensors can be placed in integrated circuits to extract a signature ofthe power dissipated by the adjacent circuit blocks built in the same silicon die. This review paper firstdiscusses the singularity that differential temperature sensors provide with respect to other sensortopologies, with circuit monitoring being their main application. The paper focuses on the monitoringof radio-frequency analog circuits. The strategies to extract the power signature of the monitoredcircuit are reviewed, and a list of application examples in the domain of test and characterizationis provided. As a practical example, we elaborate the design methodology to conceive, step bystep, a differential temperature sensor to monitor the aging degradation in a class-A linear poweramplifier working in the 2.4 GHz Industrial Scientific Medical—ISM—band. It is discussed how,for this particular application, a sensor with a temperature resolution of 0.02 K and a high dynamicrange is required. A circuit solution for this objective is proposed, as well as recommendations for thedimensions and location of the devices that form the temperature sensor. The paper concludes with adescription of a simple procedure to monitor time variability.Postprint (published version
Quasi-digital low-dropout voltage regulators uses controlled pass transistors
This article presents a low quiescent current output capacitorless quasi-digital CMOS LDO regulator with controlled pass transistors according to load demands. The pass transistor of the LDO is broken up to two smaller sizes based on a breakup criterion defined here, which considers the maximum output voltage variations to different load current steps to find the suitable current boundary for breaking up. This criterion shows that low load conditions will cause more output variations and settling time if the pass transistor is used in its maximum size. Therefore, using one smaller transistor for low load currents, and another one larger for higher currents, is the best trade-off between output variations, complexity, and power dissipation. The proposed LDO regulator has been designed and post-simulated in HSPICE in a 0.35 µm CMOS process to supply a load current between 0-100 mA while consumes 7.6 µA quiescent current. The results reveal 46% and 69% improvement on the output voltage variations and settling time, respectively.Postprint (published version
Design of two-stage class AB CMOS buffers: a systematic approach
A systematic approach for the design of two-stage class AB CMOS unity-gain buffers is proposed. It is based on the inclusion of a class AB operation to class A Miller amplifier topologies in unity-gain negative feedback by a simple technique that does not modify quiescent currents, supply requirements, noise performance, or static power. Three design examples are fabricated in a 0.5 μm CMOS process. Measurement results show slew rate improvement factors of approximately 100 for the class AB buffers versus their class A counterparts for the same quiescent power consumption (< 200 μW)
Design of a High Performance Silicon Carbide CMOS Operational Amplifier
This thesis presents the design, simulation, layout and test results of a silicon carbide (SiC) CMOS two-stage operational amplifier (op amp) with NMOS input stage. The circuit has been designed to provide a stable open-loop voltage gain (60 dB), unity-gain bandwidth (around 5 MHz) and maintain a high CMRR and PSRR within a useful input common mode range over process corners and a wide temperature range (25 °C - 300 °C). Between the two stages a Miller compensation topology is placed to improve the phase margin (around 45°). Due to the comparatively high threshold voltage values of transistors in SiC, the power supply is maintained at 15 V. There is a maximum of 21% variation in DC gain from 25 °C to 275 °C and the unity-gain bandwidth and slew rate improves with higher temperature. The major application area of this op amp is in high temperature environments where silicon (Si) integrated circuits (IC) fail to perform. In addition, the design of a second version of the operational amplifier is covered, which aims to provide more functionality and improved performance
Class-AB rail-to-rail CMOS buffer with bulk-driven super source followers
This paper describes a rail-to-rail CMOS analog voltage buffer designed to have extremely low static current consumption as well as high current drive capability. The buffer employs a complementary pair of super source followers, but a bulk-driven input device with the replica-biased scheme is utilized to eliminate the DC level shift, quasi-floating gate transistors to achieve class-AB performance, and a current switch which shifts between the complementary pair to allow rail-to-rail operation. The proposed buffer has been designed for a 0.35 mum CMOS technology to operate at a 1.8 V supply voltage. The simulated results are provided to demonstrate that the total harmonic distortion for a 1.6 Vpp 100 kHz sine wave with a 68 pF load is as low as -46 dB, whilst the static current consumption remains under 8 muA
Bulk-driven flipped voltage follower
A voltage buffer so-called the bulk-driven flipped voltage follower is presented. This proposal is based on the flipped voltage follower (FVF) technique, but a bulk-driven MOSFET with the replica-biased scheme is utilized for the input device to eliminate the DC level shift. The proposed buffer has been designed and simulated with a 0.35 mum CMOS technology. The input current and capacitance of our proposal are 1.5 pA and 9.3 fF respectively, and with 0.8 V peak-to-peak 500 kHz input, the total harmonic distortion is 0.5% for a 10 pF load. This circuit can operate from a single 1.2 V power supply and consumes only 2.5 muA
- …