Design of Low-Power NRZ/PAM-4 Wireline Transmitters

Rapid growing demand for instant multimedia access in a myriad of digital devices has pushed the need for higher bandwidth in modern communication hardwares ranging from short-reach (SR) memory/storage interfaces to long-reach (LR) data center Ethernets. At the same time, comprehensive design optimization of link system that meets the energy-efficiency is required for mobile computing and low operational cost at datacenters. This doctoral study consists of design of two low-swing wireline transmitters featuring a low-power clock distribution and 2-tap equalization in energy-efficient manners up to 20-Gb/s operation. In spite of the reduced signaling power in the voltage-mode (VM) transmit driver, the presence of the segment selection logic still diminishes the power saving benefit. The first work presents a scalable VM transmitter which offers low static power dissipation and adopts an impedance-modulated 2-tap equalizer with analog tap control, thereby obviating driver segmentation and reducing pre-driver complexity and dynamic power. Per-channel quadrature clock generation with injection-locked oscillators (ILO) allows the generation of rail-to-rail quadrature clocks. Energy efficiency is further improved with capacitively driven low-swing global clock distribution and supply scaling at lower data rates, while output eye quality is maintained at low voltages with automatic phase calibration of the local ILO-generated quarter-rate clocks. A prototype fabricated in a general purpose 65 nm CMOS process includes a 2 mm global clock distribution network and two transmitters that support an output swing range of 100-300mV with up to 12-dB of equalization. The transmitters achieve 8-16 Gb/s operation at 0.65-1.05 pJ/b energy efficiency. The second work involves a dual-mode NRZ/PAM-4 differential low-swing voltage-mode (VM) transmitter. The pulse-selected output multiplexing allows reduction of power supply and deterministic jitter caused by large on-chip parasitic inherent in the transmission-gate-based multiplexers in the earlier work. Analog impedance control replica circuits running in the background produce gate-biasing voltages that control the peaking ratio for 2-tap feed-forward equalization and PAM-4 symbol levels for high-linearity. This analog control also allows for efficient generation of the middle levels in PAM-4 operation with good linearity quantified by level separation mismatch ratio of 95%. In NRZ mode, 2-tap feedforward equalization is configurable in high-performance controlled-impedance or energy-efficient impedance-modulated settings to provide performance scalability. Analytic design consideration on dynamic power, data-rate, mismatch, and output swing brings optimal performance metric on the given technology node. The proof-of-concept prototype is verified on silicon with 65 nm CMOS process with improved performance in speed and energy-efficiency owing to double-stack NMOS transistors in the output stage. The transmitter consumes as low as 29.6mW in 20-Gb/s NRZ and 25.5mW in the 28-Gb/s PAM-4 operations

Design Techniques for Energy Efficient Multi-GB/S Serial I/O Transceivers

Total I/O bandwidth demand is growing in high-performance systems due to the emergence of many-core microprocessors and in mobile devices to support the next generation of multi-media features. High-speed serial I/O energy efficiency must improve in order to enable continued scaling of these parallel computing platforms in applications ranging from data centers to smart mobile devices. The first work, a low-power forwarded-clock I/O transceiver architecture is presented that employs a high degree of output/input multiplexing, supply-voltage scaling with data rate, and low-voltage circuit techniques to enable low-power operation. The transmitter utilizes a 4:1 output multiplexing voltage-mode driver along with 4-phase clocking that is efficiently generated from a passive poly-phase filter. The output driver voltage swing is accurately controlled from 100-200 mV_(ppd) using a low-voltage pseudo-differential regulator that employs a partial negative-resistance load for improved low frequency gain. 1:8 input de-multiplexing is performed at the receiver equalizer output with 8 parallel input samplers clocked from an 8-phase injection-locked oscillator that provides more than 1UI de-skew range. Low-power high-speed serial I/O transmitters which include equalization to compensate for channel frequency dependent loss are required to meet the aggressive link energy efficiency targets of future systems. The second work presents a low power serial link transmitter design that utilizes an output stage which combines a voltage-mode driver, which offers low static-power dissipation, and current-mode equalization, which offers low complexity and dynamic-power dissipation. The utilization of current-mode equalization decouples the equalization settings and termination impedance, allowing for a significant reduction in pre-driver complexity relative to segmented voltage-mode drivers. Proper transmitter series termination is set with an impedance control loop which adjusts the on-resistance of the output transistors in the driver voltage-mode portion. Further reductions in dynamic power dissipation are achieved through scaling the serializer and local clock distribution supply with data rate. Finally, it presents that a scalable quarter-rate transmitter employs an analog-controlled impedance-modulated 2-tap voltage-mode equalizer and achieves fast power-state transitioning with a replica-biased regulator and ILO clock generation. Capacitively-driven 2 mm global clock distribution and automatic phase calibration allows for aggressive supply scaling

Electronic identification systems for asset management

Electronic identification is an increasingly pervasive technology that permits rapid data recovery from low-power transponders whenever they are placed within the vicinity of an interrogator device. Fundamental benefits include proximity detection not requiring line-of-sight, multiple transponder access and data security. In this document, electronic identification methods for asset management are devised for the new target application of electrical appliance testing. In this application mains-powered apparatus are periodically subjected a prescribed series of electrical tests performed by a Portable Appliance Tester (PAT). The intention is to enhance the process of appliance identification and management, and to automate the test process as far as possible. Three principal methods of electronic identification were designed and analysed for this application: proximity Radio Frequency Identification (RFID), cable RFID and power- line signalling. Each method relies on an inductively coupled mechanism that utilities a signalling technique called direct-load modulation. This is particularly suited to low- cost passive transponder designs. Physical limitations to proximity RFID are identified including coil size, orientation and susceptibility to nearby conducting surfaces. A novel inductive signalling method called cable RFID is then described that permits automatic appliance identification. This method uses the appliance power cable and inlet filter to establish a communication channel between interrogator and transponder. Prior to commencing the test phase, an appliance is plugged into the PAT and identified automatically via cable RFID. An attempt is made to extend the scope of cable RFID by developing a novel mains power-line signalling method that uses direct-load modulation and passive transponders. Finally, two different implementations of RFID interrogator are described. The first takes the form of an embeddable module intended for incorporation into electronic identification products such as RFID enabled PAT units. Software Defined Radio (SDR) principles are applied to the second interrogator design in an effort to render the device reconfigurable

Design of a Triple-Mode Low Power Single-Ended Source-Series-Terminated Driver

In data centers, the multi-mode fiber (MMF) links and vertical cavity surface emitting laser (VCSEL) diode are widely used for short-reach optical communications (< 100 m) because of their low cost and their ability to handle the ever-increasing data rates. In conventional VCSEL drivers, the laser diode driver (LDD) can be bonded to a chip carrier, while the host chip is bonded to another chip carrier. This host chip contains an electrical link driver and is connected to the VCSEL driver via a short electrical link. To reduce the overall power consumption of the conventional VCSEL driver system, the electrical link driver in the host chip can be modified so that it can drive the VCSEL diode directly, eliminating the laser diode driver. Thus, the modified driver can drive either an electrical link or a VCSEL diode. By modifying the packaging, the VCSEL diode can be wire bonded to the host chip and directly driven. Driving a VCSEL diode requires features such as asymmetric equalization, relatively low modulation current, and DC current source to bias the VCSEL. On the other hand, driving an electrical link requires symmetric equalization, relatively high output voltage swing from the driver, and matched output impedance. Accordingly, a typical electrical link driver cannot drive a VCSEL diode and the VCSEL driver is not suitable for driving an electrical link. The proposed design is a single-ended source-series-terminated (SST) voltage-mode driver in a CMOS 65 nm technology with three driving modes: driving electrical links with losses up to 16 dB (mode I), driving VCSEL diodes through a short electrical link (mode II), and driving VCSEL diodes directly wire bonded to the driver (mode III). The proposed design provides a tunable output swing without changing the driver output impedance and achieves a smooth transition between symmetric and asymmetric equalization as needed. In simulation, the proposed triple-mode driver operates up to a bit rate of 20 Gb/s, and dissipates at most 27.6 mW of power when operating at mode II when using a supply voltage of 1.2 V

System-level design, simulation and measurement for high-speed data links

The era of the internet-of-things (IOT) is expanding the utilization of mobile and cloud computing to a global scale. The enormous data transport places a huge design overhead in building low-cost, low-power, low-error-rate high-speed data links. This thesis provides a system-level overview of the design, simulation, and measurement of high-speed digital applications in the context of signal integrity. Examples are provided to demonstrate the design approach and trade-offs made to arrive at the results. Modeling and simulation methodologies for high-speed interconnect are discussed and studied, using both conformal mapping and the variational method in closed-form solutions, with examples provided to study the frequency-dependent channel effects in high-speed digital systems. Detailed processes along with examples are presented at the end to illustrate some real-world issues many engineers will face when characterizing and measuring high-speed data links

High Speed Reconfigurable NRZ/PAM4 Transceiver Design Techniques

While the majority of wireline standards use simple binary non-return-to-zero (NRZ) signaling, four-level pulse-amplitude modulation (PAM4) standards are emerging to increase bandwidth density. This dissertation proposes efficient implementations for high speed NRZ/PAM4 transceivers. The first prototype includes a dual-mode NRZ/PAM4 serial I/O transmitter which can support both modulations with minimum power and hardware overhead. A source-series-terminated (SST) transmitter achieves 1.2Vpp output swing and employs lookup table (LUT) control of a 31-segment output digital-to-analog converter (DAC) to implement 4/2-tap feed-forward equalization (FFE) in NRZ/PAM4 modes, respectively. Transmitter power is improved with low-overhead analog impedance control in the DAC cells and a quarter-rate serializer based on a tri-state inverter-based mux with dynamic pre-driver gates. The transmitter is designed to work with a receiver that implements an NRZ/PAM4 decision feedback equalizer (DFE) that employs 1 finite impulse response (FIR) and 2 infinite impulse response (IIR) taps for first post-cursor and long-tail ISI cancellation, respectively. Fabricated in GP 65-nm CMOS, the transmitter occupies 0.060mm² area and achieves 16Gb/s NRZ and 32Gb/s PAM4 operation at 10.4 and 4.9 mW/Gb/s while operating over channels with 27.6 and 13.5dB loss at Nyquist, respectively. The second prototype presents a 56Gb/s four-level pulse amplitude modulation (PAM4) quarter-rate wireline receiver which is implemented in a 65nm CMOS process. The frontend utilize a single stage continuous time linear equalizer (CTLE) to boost the main cursor and relax the pre-cursor cancelation requirement, requiring only a 2-tap pre-cursor feed-forward equalization (FFE) on the transmitter side. A 2-tap decision feedback equalizer (DFE) with one finite impulse response (FIR) tap and one infinite impulse response (IIR) tap is employed to cancel first post-cursor and longtail inter-symbol interference (ISI). The FIR tap direct feedback is implemented inside the CML slicers to relax the critical timing of DFE and maximize the achievable data-rate. In addition to the per-slice main 3 data samplers, an error sampler is utilized for background threshold control and an edge-based sampler performs both PLL-based CDR phase detection and generates information for background DFE tap adaptation. The receiver consumes 4.63mW/Gb/s and compensates for up to 20.8dB loss when operated with a 2- tap FFE transmitter. The experimental results and comparison with state-of-the-art shows superior power efficiency of the presented prototypes for similar data-rate and channel loss. The usage of proposed design techniques are not limited to these specific prototypes and can be applied for any wireline transceiver with different modulation, data-rate and CMOS technology

Communication and energy delivery architectures for personal medical devices

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.Cataloged from PDF version of thesis.Includes bibliographical references (p. 219-232).Advances in sensor technologies and integrated electronics are revolutionizing how humans access and receive healthcare. However, many envisioned wearable or implantable systems are not deployable in practice due to high energy consumption and anatomically-limited size constraints, necessitating large form-factors for external devices, or eventual surgical re-implantation procedures for in-vivo applications. Since communication and energy-management sub-systems often dominate the power budgets of personal biomedical devices, this thesis explores alternative usecases, system architectures, and circuit solutions to reduce their energy burden. For wearable applications, a system-on-chip is designed that both communicates and delivers power over an eTextiles network. The transmitter and receiver front-ends are at least an order of magnitude more efficient than conventional body-area networks. For implantable applications, two separate systems are proposed that avoid reimplantation requirements. The first system extracts energy from the endocochlear potential, an electrochemical gradient found naturally within the inner-ear of mammals, in order to power a wireless sensor. Since extractable energy levels are limited, novel sensing, communication, and energy management solutions are proposed that leverage duty-cycling to achieve enabling power consumptions that are at least an order of magnitude lower than previous work. Clinical measurements show the first system demonstrated to sustain itself with a mammalian-generated electrochemical potential operating as the only source of energy into the system. The second system leverages the essentially unlimited number of re-charge cycles offered by ultracapacitors. To ease patient usability, a rapid wireless capacitor charging architecture is proposed that employs a multi-tapped secondary inductive coil to provide charging times that are significantly faster than conventional approaches.by Patrick Philip Mercier.Ph.D