Arrayable Voltage-Controlled Ring-Oscillator for Direct Time-of-Flight Image Sensors

Direct time-of-flight (d-ToF) estimation with high frame rate requires the incorporation of a time-to-digital converter (TDC) at pixel level. A feasible approach to a compact implementation of the TDC is to use the multiple phases of a voltage-controlled ring-oscillator (VCRO) for the finest bits. The VCRO becomes central in determining the performance parameters of a d-ToF image sensor. In this paper, we are covering the modeling, design, and measurement of a CMOS pseudo-differential VCRO. The oscillation frequency, the jitter due to mismatches and noise and the power consumption are analytically evaluated. This design has been incorporated into a 64x64-pixel array. It has been fabricated in a 0.18 mu m standard CMOS technology. Occupation area is 28x29 mu m(2) and power consumption is 1.17 mW at 850 MHz. The measured gain of the VCRO is of 477 MHz/V with a frequency tuning range of 53%. Moreover, it features a linearity of 99.4% over a wide range of control frequencies, namely, from 400 to 850 MHz. The phase noise is of -102 dBc/Hz at 2 MHz offset frequency from 850 MHz. The influence of these parameters in the performance of the TDC has been measured. The minimum time bin of the TDC is 147 ps with a rms DNL/INL of 0.13/1.7LSB.Office of Naval Research (USA) N000141410355Ministerio de Economía y Competitividad TEC2015-66878-C3-1-RJunta de Andalucía P12-TIC 233

VLSI Implementation of TDC Architectures Used in PET Imaging Systems

Positron emission tomography (PET) is a medical imaging method based on the measurement of concentrations of positron-emitting radionuclides in a living body. In the PET imaging system, glucose is labeled with a positron-emitting radionuclide and injected intravenously. Then, the positrons move through the tissue and collide with the electrons of the cells in which they interact. As a result of this interaction, two gamma rays are emitted in the opposite direction. Gama rays emitted from cancerous tissue that has retained radioactive glucose are detected through ring-shaped detectors. And the detected signals are converted into an electrical response. Subsequently, these responses are sampled with electronic circuits and recorded as histogram matrix to generate the image set. The gamma rays may not reach the detectors located in the opposite position in equal time. In PETs having TOF characteristics, it is aimed to obtain better positioning information by a method based on the principle of measuring the difference between the reach time of the two photons to detectors. The measurement of the flight time is carried out with TDC structures. The measurement of this time difference at the ps level is directly related to the spatial resolution of the PET system. In this study, 45 nm CMOS VLSI simulations of TDC structures that have various architectural approaches were performed for use in PET systems. With the designed TDC architectures, two gamma photons time reach to detectors have been simulated and the time difference has been successfully digitized. In addition, various performance metrics such as input and output voltages, time resolutions, measurement ranges, and power analysis of TDC architectures have been determined. Proposed Vernier oscillator-based TDC architecture has been reached 25 ps time resolution with a low power consumption of 1.62681 mW at 1V supply voltage.Comment: 8 pages, in Turkish language. 6 figures, conference paper,International Marmara Sciences Congess (IMASCON 2019 SPRING), https://www.imascon.com/dosyalar/imascon2019bahar/imascon_fen_bildiriler_ciltII_bahar_2019.pdf , https://avesis.kocaeli.edu.tr/yayin/99073ee1-45ff-495e-9cab-42de4d0fad71/vlsi-implementation-of-tdc-architectures-used-in-pet-imaging-system

VERNIER RING OSCILLATOR TYPE FIRST ORDER DELTA-SIGMA TDC WITH COUNTERT AND DELAY LINE

In this paper, we propose All Digital Vernier Ring Oscillator type Delta-Sigma Time-to-Digital Converter (ΔΣVROTDC) with counter and delay. The system achieves feedback by counter and delay line. This design reduces noise on feedback signal. The proposed system designed and simulated by MATLAB/simulink. Proposed system achieves first order noise shaping of quantization noise and simulated a signal to noise ratio (SNR) of 65.3 dB

A 1.9 ps-rms Precision Time-to-Amplitude Converter With 782 fs LSB and 0.79%-rms DNL

Measuring a time interval in the nanoseconds range has opened the way to 3-D imaging, where additional information as distance of objects light detection and ranging (LiDAR) or lifetime decay fluorescence-lifetime imaging (FLIM) is added to spatial coordinates. One of the key elements of these systems is the time measurement circuit, which encodes a time interval into digital words. Nowadays, most demanding applications, especially in the biological field, require time-conversion circuits with a challenging combination of performance, including sub-ps resolution, ps precision, several ns of measurement range, linearity better than few percent of the bin width (especially when complex lifetime data caused by multiple factors have to be retrieved), and operating rates in the order of tens of Mcps. In this article, we present a time-to-amplitude converter (TAC) implemented in a SiGe 350 nm process featuring a resolution of 782 fs, a minimum timing jitter as low as 1.9 ps-rms, a DNL down to 0.79% LSB-rms, and conversion rate as high as 12.3 Mcps. With an area occupation of 0.2 mm2 [without PADs and digital-to-analog converter (DAC)], a FSR up to 100 ns, and a power dissipation of 70 mW, we developed a circuit suitable to be the core element of a densely integrated, faster and high-performance system

Multi-channel, low nonlinearity time-to-digital converters based on 20nm and 28nm FPGAs

Abstract—This paper presents low nonlinearity, compact and multi-channel time-to-digital converters (TDC) in Xilinx 28nm Virtex 7 and 20nm UltraScale FPGAs. The proposed TDCs integrate several innovative methods that we have developed: 1) the sub-tapped delay line (TDL) averaging topology, 2) tap timing tests, 3) a direct compensation architecture and 4) a mixed calibration method. The code density tests show that the proposed TDCs have much better linearity performances than previously reported ones. Our approach is cost-effective in terms of the consumption of logic resources. To demonstrate this, we implemented 96 channel TDCs in both FPGAs, using less than 25 % of the logic resources. The achieved least significant bit (LSB) is 10.5ps for Virtex 7 and 5.0 ps for UltraScale FPGAs. After the compensation and calibration, the differential nonlinearity (DNL) is within [-0.05, 0.08] LSB with σDNL = 0.01 LSB, and the integral nonlinearity (INL) is within [-0.09, 0.11] LSB with σINL = 0.04 LSB for the Virtex 7 FPGA. The DNL is within [-0.12, 0.11] LSB with σDNL = 0.03 LSB, and the INL is within [-0.15, 0.48] LSB with σINL = 0.20 LSB for the UltraScale FPGA

Design of CMOS Digital Silicon Photomultipliers with ToF for Positron Emission Tomography

This thesis presents a contribution to the design of single-photon detectors for medical imaging. Specifically, the focus has been on the development of a pixel capable of single-photon counting in CMOS technology, and the associated sensor thereof. These sensors can work under low light conditions and provide timing information to determine the time-stamp of the incoming photons. For instance, this is particularly attractive for applications that rely either on time-of-flight measurements or on exponential decay determination of the light source, like positron emission tomography or fluorescence-lifetime imaging, respectively. This thesis proposes the study of the pixel architecture to optimize its performance in terms of sensitivity, linearity and signal to noise ratio. The design of the pixel has followed a bottom-up approach, taking care of the smallest building block and studying how the different architecture choices affect performance. Among the various building blocks needed, special emphasis has been placed on the following: • the Single-Photon Avalanche Diode (SPAD), a photodiode able to detect photons one by one; • the front-end circuitry of this diode, commonly called quenching and recharge circuit; • the Time-to-Digital Converter (TDC), which determines the timing performance of the pixel. The proposed architectural exploration provides a comprehensive insight into the design space of the pixel, allowing to determine the optimum design points in terms of sensor sensitivity, linearity or signal to noise ratio, thus helping designers to navigate through non-straightforward trade-offs. The proposed TDC is based on a voltage-controlled ring oscillator, since this architecture provides moderate time resolutions while keeping the footprint, the power, and conversion time relatively small. Two pseudo-differential delay stages have been studied, one with cross-coupled PMOS transistors and the other with cross-coupled inverters. Analytical studies and simulations have shown that cross-coupled inverters are the most appropriate to implement the TDC because they achieve better time resolution with smaller energy per conversion than cross-coupled PMOS transistor stages. A 1.3×1.3 mm2 pixel has been implemented in an 110 nm CMOS image sensor technology, to have the benefits of sub-micron technologies along with the cleanliness of CMOS image sensor technologies. The fabricated chips have been used to characterize the single-photon avalanche diodes. The results agree with expectations: a maximum photon detection probability of 46 % and a median dark count rate of 0.4 Hz/µm2 with an excess voltage of 3 V. Furthermore, the characterization of the TDC shows that the time resolution is below 100 ps, which agrees with post-layout simulations. The differential non-linearity is ±0.4LSB, and the integral non-linearity is ±6.1LSB. Photoemission occurs during characterization - an indication that the avalanches are not quenched properly. The cause of this has been identified to be in the design of the SPAD and the quenching circuit. SPADs are sensitive devices which maximum reverse current must be well defined and limited by the quenching circuit, otherwise unwanted effects like excessive cross-talk, noise, and power consumption may happen. Although this issue limits the operation of the implemented pixel, the information obtained during the characterization will help to avoid mistakes in future implementations

Fifth International Microgravity Combustion Workshop

This conference proceedings document is a compilation of 120 papers presented orally or as poster displays to the Fifth International Microgravity Combustion Workshop held in Cleveland, Ohio on May 18-20, 1999. The purpose of the workshop is to present and exchange research results from theoretical and experimental work in combustion science using the reduced-gravity environment as a research tool. The results are contributed by researchers funded by NASA throughout the United States at universities, industry and government research agencies, and by researchers from at least eight international partner countries that are also participating in the microgravity combustion science research discipline. These research results are intended for use by public and private sector organizations for academic purposes, for the development of technologies needed for the Human Exploration and Development of Space, and to improve Earth-bound combustion and fire-safety related technologies