Time-based, Low-power, Low-offset 5-bit 1 GS/s Flash ADC Design in 65nm CMOS Technology

Low-power, medium resolution, high-speed analog-to-digital converters (ADCs) have always been important block which have abundant applications such as digital signal processors (DSP), imaging sensors, environmental and biomedical monitoring devices. This study presents a low power Flash ADC designed in nanometer complementary metal-oxide semiconductors (CMOS) technology. Time analysis on the output delay of the comparators helps to generate one more bit. The proposed technique reduced the power consumption and chip area substantially in comparison to the previous state-of-the-art work. The proposed ADC was developed in TSMC 65nm CMOS technology. The offset cancellation technique was embedded in the proposed comparator to decrement the static offset of the comparator. Moreover, one more bit was generated without using extra comparators. The proposed ADC achieved 4.1 bits ENOB at input Nyquist frequency. The simulated differential and integral non-linearity static tests were equal to +0.26/-0.17 and +0.22/-0.15, respectively. The ADC consumed 7.7 mW at 1 GHz sampling frequency, achieving 415 fJ/Convstep Figure of Merit (FoM)

Design and Optimization of Low-power Level-crossing ADCs

This thesis investigates some of the practical issues related to the implementation of level-crossing ADCs in nanometer CMOS. A level-crossing ADC targeting minimum power is designed and measured. Three techniques to circumvent performance limitations due to the zero-crossing detector at the heart of the ADC are proposed and demonstrated: an adaptive resolution algorithm, an adaptive bias current algorithm, and automatic offset cancelation. The ADC, fabricated in 130 nm CMOS, is designed to operate over a 20 kHz bandwidth while consuming a maximum of 8.5 uW. A peak SNDR of 54 dB for this 8-bit ADC demonstrates a key advantage of level-crossing sampling, namely SNDR higher than the classic Nyquist limit

Continuous-Time and Companding Digital Signal Processors Using Adaptivity and Asynchronous Techniques

The fully synchronous approach has been the norm for digital signal processors (DSPs) for many decades. Due to its simplicity, the classical DSP structure has been used in many applications. However, due to its rigid discrete-time operation, a classical DSP has limited efficiency or inadequate resolution for some emerging applications, such as processing of multimedia and biological signals. This thesis proposes fundamentally new approaches to designing DSPs, which are different from the classical scheme. The defining characteristic of all new DSPs examined in this thesis is the notion of "adaptivity" or "adaptability." Adaptive DSPs dynamically change their behavior to adjust to some property of their input stream, for example the rate of change of the input. This thesis presents both enhancements to existing adaptive DSPs, as well as new adaptive DSPs. The main class of DSPs that are examined throughout the thesis are continuous-time (CT) DSPs. CT DSPs are clock-less and event-driven; they naturally adapt their activity and power consumption to the rate of their inputs. The absence of a clock also provides a complete avoidance of aliasing in the frequency domain, hence improved signal fidelity. The core of this thesis deals with the complete and systematic design of a truly general-purpose CT DSP. A scalable design methodology for CT DSPs is presented. This leads to the main contribution of this thesis, namely a new CT DSP chip. This chip is the first general-purpose CT DSP chip, able to process many different classes of CT and synchronous signals. The chip has the property of handling various types of signals, i.e. various different digital modulations, both synchronous and asynchronous, without requiring any reconfiguration; such property is presented for the first time CT DSPs and is impossible for classical DSPs. As opposed to previous CT DSPs, which were limited to using only one type of digital format, and whose design was hard to scale for different bandwidths and bit-widths, this chip has a formal, robust and scalable design, due to the systematic usage of asynchronous design techniques. The second contribution of this thesis is a complete methodology to design adaptive delay lines. In particular, it is shown how to make the granularity, i.e. the number of stages, adaptive in a real-time delay line. Adaptive granularity brings about a significant improvement in the line's power consumption, up to 70% as reported by simulations on two design examples. This enhancement can have a direct large power impact on any CT DSP, since a delay line consumes the majority of a CT DSP's power. The robust methodology presented in this thesis allows safe dynamic reconfiguration of the line's granularity, on-the-fly and according to the input traffic. As a final contribution, the thesis also examines two additional DSPs: one operating the CT domain and one using the companding technique. The former operates only on level-crossing samples; the proposed methodology shows a potential for high-quality outputs by using a complex interpolation function. Finally, a companding DSP is presented for MPEG audio. Companding DSPs adapt their dynamic range to the amplitude of their input; the resulting can offer high-quality outputs even for small inputs. By applying companding to MPEG DSPs, it is shown how the DSP distortion can be made almost inaudible, without requiring complex arithmetic hardware

Time-Based Analog to Digital Converters.

Low-power, small analog-to-digital converters (ADCs) have numerous applications in areas ranging from power-aware wireless sensing nodes for environmental monitoring to biomedical monitoring devices in point-of-care (PoC) instruments. The work focuses on ultra-low-power, and highly integrated implementations of ADCs, in nanometer-scale complementary metal-oxide-semiconductor (CMOS) very large scale (VLSI) integrated circuit fabrication technologies. In particular, we explore time-based techniques for data conversion, which can potentially achieve significant reductions in power consumption while keeping silicon chip area small, compared to today’s state-of-the-art ADC architectures. Today, digital integrated circuits and digital signal processors (DSP) are taking advantage of technology scaling to achieve improvements power, speed, and cost. Meanwhile, as technology scaling reduces supply voltage and intrinsic transistor gain, analog circuit designers face disadvantages. With these disadvantages of technology scaling, two new broad trends have emerged in ADC research. The first trend is the emergence of digitally-assisted analog design, which emphasizes the relaxation of analog domain precision and the recovering accuracy (and performance) in the digital domain. This approach is a good match to the capabilities of fine line technology and helps to reduce power consumption. The second trend is the representation of signals, and the processing of signals, in the time domain. Technology scaling and its focus on high-performance digital systems offers better time resolution by reducing the gate delay. Therefore, if we represent a signal as a period of time, rather than as a voltage, we can take advantage of technology scaling, and potentially reduce power consumption and die area. This thesis focuses on pulse position modulation (PPM) ADCs, which incorporate time-domain processing and digitally assisted analog circuitry. This architecture reduces power consumption and area significantly, without sacrificing performance. The input signal is pulse position modulated and the analog information is carried in the form of timing intervals. Timing measurement accuracy presents a major challenge and we present various methods in which accuracy can be achieved using CMOS processes. This ‘digital’ approach is more power efficient compared with pure analog solutions, utilized for amplitude measurement of input signals.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/64787/1/naraghi_1.pd

Power efficient, event driven data acquisition and processing using asynchronous techniques

PhD ThesisData acquisition systems used in remote environmental monitoring equipment and biological sensor nodes rely on limited energy supply soured from either energy harvesters or battery to perform their functions. Among the building blocks of these systems are power hungry Analogue to Digital Converters and Digital Signal Processors which acquire and process samples at predetermined rates regardless of the monitored signal’s behavior. In this work we investigate power efficient event driven data acquisition and processing techniques by implementing an asynchronous ADC and an event driven power gated Finite Impulse Response (FIR) filter. We present an event driven single slope ADC capable of generating asynchronous digital samples based on the input signal’s rate of change. It utilizes a rate of change detection circuit known as the slope detector to determine at what point the input signal is to be sampled. After a sample has been obtained it’s absolute voltage value is time encoded and passed on to a Time to Digital Converter (TDC) as part of a pulse stream. The resulting digital samples generated by the TDC are produced at a rate that exhibits the same rate of change profile as that of the input signal. The ADC is realized in 0.35mm CMOS process, covers a silicon area of 340mm by 218mm and consumes power based on the input signal’s frequency. The samples from the ADC are asynchronous in nature and exhibit random time periods between adjacent samples. In order to process such asynchronous samples we present a FIR filter that is able to successfully operate on the samples and produce the desired result. The filter also poses the ability to turn itself off in-between samples that have longer sample periods in effect saving power in the process

Low Power Circuits for Smart Flexible ECG Sensors

Cardiovascular diseases (CVDs) are the world leading cause of death. In-home heart condition monitoring effectively reduced the CVD patient hospitalization rate. Flexible electrocardiogram (ECG) sensor provides an affordable, convenient and comfortable in-home monitoring solution. The three critical building blocks of the ECG sensor i.e., analog frontend (AFE), QRS detector, and cardiac arrhythmia classifier (CAC), are studied in this research. A fully differential difference amplifier (FDDA) based AFE that employs DC-coupled input stage increases the input impedance and improves CMRR. A parasitic capacitor reuse technique is proposed to improve the noise/area efficiency and CMRR. An on-body DC bias scheme is introduced to deal with the input DC offset. Implemented in 0.35m CMOS process with an area of 0.405mm2, the proposed AFE consumes 0.9W at 1.8V and shows excellent noise effective factor of 2.55, and CMRR of 76dB. Experiment shows the proposed AFE not only picks up clean ECG signal with electrodes placed as close as 2cm under both resting and walking conditions, but also obtains the distinct -wave after eye blink from EEG recording. A personalized QRS detection algorithm is proposed to achieve an average positive prediction rate of 99.39% and sensitivity rate of 99.21%. The user-specific template avoids the complicate models and parameters used in existing algorithms while covers most situations for practical applications. The detection is based on the comparison of the correlation coefficient of the user-specific template with the ECG segment under detection. The proposed one-target clustering reduced the required loops. A continuous-in-time discrete-in-amplitude (CTDA) artificial neural network (ANN) based CAC is proposed for the smart ECG sensor. The proposed CAC achieves over 98% classification accuracy for 4 types of beats defined by AAMI (Association for the Advancement of Medical Instrumentation). The CTDA scheme significantly reduces the input sample numbers and simplifies the sample representation to one bit. Thus, the number of arithmetic operations and the ANN structure are greatly simplified. The proposed CAC is verified by FPGA and implemented in 0.18m CMOS process. Simulation results show it can operate at clock frequencies from 10KHz to 50MHz. Average power for the patient with 75bpm heart rate is 13.34W

NONUNIFORMLY SAMPLED DIGITAL SIGNAL PROCESSING FOR LOW-POWER BIOMEDICAL APPLICATIONS.

Ph.DDOCTOR OF PHILOSOPH

Energy-Efficient Time-Based Encoders and Digital Signal Processors in Continuous Time

Continuous-time (CT) data conversion and continuous-time digital signal processing (DSP) are an interesting alternative to conventional methods of signal conversion and processing. This alternative proposes time-based encoding that may not suffer from aliasing; shows superior spectral properties (e.g. no quantization noise floor); and enables time-based, event-driven, flexible signal processing using digital circuits, thus scaling well with technology. Despite these interesting features, this approach has so far been limited by the CT encoder, due to both its relatively poor energy efficiency and the constraints it imposes on the subsequent CT DSP. In this thesis, we present three principles that address these limitations and help improve the CT ADC/DSP system. First, an adaptive-resolution encoding scheme that achieves first-order reconstruction with simple circuitry is proposed. It is shown that for certain signals, the scheme can significantly reduce the number of samples generated per unit of time for a given accuracy compared to schemes based on zero-order-hold reconstruction, thus promising to lead to low dynamic power dissipation at the system level. Presented next is a novel time-based CT ADC architecture, and associated encoding scheme, that allows a compact, energy-efficient circuit implementation, and achieves first-order quantization error spectral shaping. The design of a test chip, implemented in a 0.65-V 28-nm FDSOI process, that includes this CT ADC and a 10-tap programmable FIR CT DSP to process its output is described. The system achieves 32 dB – 42 dB SNDR over a 10 MHz – 50 MHz bandwidth, occupies 0.093 mm2, and dissipates 15 µW–163 µW as the input amplitude goes from zero to full scale. Finally, an investigation into the possibility of CT encoding using voltage-controlled oscillators is undertaken, and it leads to a CT ADC/DSP system architecture composed primarily of asynchronous digital delays. The latter makes the system highly digital and technology-scaling-friendly and, hence, is particularly attractive from the point of view of technology migration. The design of a test chip, where this delay-based CT ADC/DSP system architecture is used to implement a 16-tap programmable FIR filter, in a 1.2-V 28-nm FDSOI process, is described. Simulations show that the system will achieve a 33 dB – 40 dB SNDR over a 600 MHz bandwidth, while dissipating 4 mW

Radioisotope identification with neuromorphic methodology: different solutions and evaluations

Early detection of radioisotopes plays an increasingly important role in the modern world. It allows the possibility of quick countermeasures when faced with potentially hazardous radioactive materials like dirty bombs, and nuclear leakage. This could secure the lives of the innocent in populated areas including airports, stadiums or ports. A light-weight compact handheld device could be used in this situation for the patrol team. However, the operating hours for these devices are normally constrained by the batteries they carry. More efficient al- gorithms or solutions are needed for this resource-constraint application to extend the battery life so that security patrol is not frequently interrupted by the recharge. Event-based processing is a novel technique that allows the computing unit to operate only when there is a key event while staying idle otherwise. Spiking neural network (SNN) is a promising candidate for event-based processing and also known as neuromorphic method- ology due to the biomimicry plausibility, which could be easily implemented and still offer comparable accuracy to its counterpart — artificial neural network (ANN), which is notoriously power-hungry. In this research work, it will be demonstrated that using SNN for radioisotope identification (RIID) is possible and capable of achieving the same or even better accuracy when compared with ANNs. Meanwhile, the power consumption of the proposed method on a field program- mable gate array (FPGA) shows that power reduction is highly significant compared with the old software implementation on a smartphone. The task has been delivered in two parts, we first attempted an unsupervised Spike-Timing- Dependent Plasticity (STDP) SNN implementation on SpiNNaker, an emulation platform for SNN. This demonstrates the capability of classifying radioisotopes using purely SNN compat- ible training methods and architecture. We then managed to implement a more complex bin-ratio ensemble SNN (BESNN) on FPGA with better performance. To achieve this implementation, a new SNN conversion method was created to facilitate the digital hardware implementation. This conversion flow allows the highly sparse weight matrix representation without sacrificing overall accuracy. In the meantime, the power consumption of the mentioned design has been characterised, which could be used to estimate the battery life of a handheld system while functioning. Even though this design has been validated on an FPGA, further squeeze for the power saving is possible if an application specific integrated circuits (ASIC) could be delivered. Furthermore, the analogue unit used in the design is a compromise given that the logarithm could not be done by a spiking neuron at the moment. This prevents an end-to-end application, which is preferred for higher integration and potentially more power conservation. According to our knowledge, applying neuromorphic methodology to address RIID represents uncharted territory, especially in the context of power characterisation, an aspect that has not been explored previously. This research work fills the gap that is present in the research field and also offers a functional low-power prototype for the handheld RIID device producer. This project pioneers the use of an event-based processing algorithm for radioisotope identi- fication, marking a significant advancement in the field. Leveraging Spiking Neural Networks (SNNs) on specialised hardware, the project establishes a comprehensive application flow, showcasing the efficacy and potential of SNNs in this domain. The implementation of an unsupervised STDP algorithm for radioisotope identification is also groundbreaking, introducing a local self-learning rule for complex tasks beyond handwritten digit recognition. Additionally, the bin-ratio ensemble project achieves remarkable accuracy, setting new bench- marks in the field. It represents the first ensemble SNN application in radioisotope identifica- tion, further enhanced by an innovative ANN-SNN conversion method with iterative pruning to reduce computational overhead. Furthermore, this research provides detailed insights into sparse SNN construction and char- acterises hardware implementation, shedding light on power and energy consumption con- siderations