CMOS current amplifiers : speed versus nonlinearity

This work deals with analogue integrated circuit design using various types of current-mode amplifiers. These circuits are analysed and realised using modern CMOS integration technologies. The dynamic nonlinearities of these circuits are discussed in detail as in the literature only linear nonidealities and static nonlinearities are conventionally considered. For the most important open-loop current-mode amplifier, the second-generation current-conveyor (CCII), a macromodel is derived that, unlike other reported macromodels, can accurately predict the common-mode behaviour in differential applications. Similarly, this model is used to describe the nonidealities of several other current-mode amplifiers because similar circuit structures are common in such amplifiers. With modern low-voltage CMOS-technologies, the current-mode operational amplifier and the high-gain current-conveyor (CCII∞) perform better than open-loop current-amplifiers. Similarly, unlike with conventional voltage-mode operational amplifiers, the large-signal settling behaviour of these two amplifier types does not degrade as CMOS-processes are scaled down. In this work, two 1 MHz 3rd -order low-pass continuous-time filters are realised with a 1.2 μm CMOS-process. These filters use a differential CCII∞ with linearised, dynamically biased output stages resulting in performance superior to most OTA-C filter realisations reported. Similarly, two logarithmic amplifier chips are designed and fabricated. The first circuit, implemented with a 1.2 μm BiCMOS-process, uses again a CCII∞. This circuit uses a pn-junction as a logarithmic feedback element. With a CCII∞ the constant gain-bandwidth product, typical of voltage-mode operational amplifiers, is avoided resulting in a constant 1 MHz bandwidth with a 60 dB signal amplitude range. The second current-mode logarithmic amplifier, based on piece-wise linear approximation of the logarithmic function by a cascade of limiting current amplifier stages, is realised in a standard 1.2 μm CMOS-process. The limiting level in these current amplifiers is less sensitive to process variation than in limiting voltage amplifiers resulting in exceptionally low temperature dependency of the logarithmic output signal. Additionally, along with this logarithmic amplifier a new current peak detectoris developed.reviewe

Design of PVT Tolerant Inverter Based Circuits for Low Supply Voltages

University of Minnesota Ph.D. dissertation. June 2015. Major: Electrical Engineering. Advisor: Ramesh Harjani. 1 computer file (PDF); xiv, 187 pages.Rapid advances in the field of integrated circuit design has been advantageous from the point of view of cost and miniaturization. Although technology scaling is advantageous to digital circuits in terms of increased speed and lower power, analog circuits strongly suffer from this trend. This is becoming a crucial bottle neck in the realization of a system on chip in scaled technology merging high-density digital parts, with high performance analog interfaces. This is because scaled technologies reduce the output impedance (gain) and supply voltage which limits the dynamic range (output swing). One way to mitigate the power supply restrictions is to move to current mode circuit circuit design rather than voltage mode designs. This thesis focuses on designing Process Voltage and Temperature (PVT) tolerant base band circuits at lower supply voltages and in lower technologies. Inverter amplifiers are known to have better transconductance efficiency, better noise and linearity performance. But inverters are prone to PVT variations and has poor CMRR and PSRR. To circumvent the problem, we have proposed various biasing schemes for inverter like semi constant current biasing, constant current biasing and constant gm biasing. Each biasing technique has its own advantages, like semi constant current biasing allows to select different PMOS and NMOS current. This feature allows for higher inherent inverter linearity. Similarly constant current and constant gm biasing allows for reduced PVT sensitivity. The inverter based OTA achieves a measured THD of -90.6 dB, SNR of 78.7 dB, CMRR 97dB, PSRR 61 dB wile operating from a nominal power of 0.9V and at output swing of 0.9V{pp,diff} in TSMC 40nm general purpose process. Further the measured third harmonic distortion varies approximately by 11.5dB with 120C variation in temperature and 9dB with a 18% variation in supply voltage. The linearity can be increased by increasing the loop gain and bandwidth in a negative feedback circuit or by increasing the over drive voltage in open loop architectures. However both these techniques increases the noise contribution of the circuit. There exist a trade off between noise and linearity in analog circuits. To circumvent this problem, we have introduced nonlinear cancellation techniques and noise filtering techniques. An analog-to-digital converter (ADC) driver which is capable of amplifying the continuous time signal with a gain of 8 and sample onto the input capacitor(1pF) of 1 10 bit successive approximation register (SAR) ADC is designed in TSMC 65nm general purpose process. This exploits the non linearity cancellation in current mirror and also allows for higher bandwidth operation by decoupling closed loop gain from the negative feedback loop. The noise from the out of band is filtered before sampling leading to low noise operation. The measured design operates at 100MS/s and has an OIP_3 of 40dBm at the nyquist rate, noise power spectral density of 17nV/sqrt{Hz} and inter modulation distortion of 65dB. The intermodulation distortion variation across 10 chips is 6dB and 4dB across a temperature variation of 120C. Non linearity cancellation is exploited in designing two filters, an anti alias filter and a continuously tunable channel select filter. Traditional active RC filters are based on cascade of integrators. These create multiple low impedance nodes in the circuit which results in a higher noise. We propose a real low pass filter based filter architecture rather than traditional integrator based approach. Further the entire filtering operation takes place in current domain to circumvent the power supply limitations. This also facilitates the use of tunable non linear metal oxide semiconductor capacitor (MOSCAP) as filter capacitors. We introduce techniques of self compensation to use the filter resistor and capacitor as compensation capacitor for lower power. The anti alias filter designed for 50MHz bandwidth is fabricated in IBM 65nm process achieves an IIP3 of 33dBm, while consuming 1.56mW from 1.2 V supply. The channel select filter is tunable from 34MHz to 314MHz and is fabricated in TSMC 65nm general purpose process. This filter achieves an OIP3 of 25.24 dBm at the maximum frequency while drawing 4.2mA from 1.1V supply. The measured intermodulation distortion varies by 5dB across 120C variation in temperature and 6.5dB across a 200mV variation in power supply. Further this filter presents a high impedance node at the input and a low impedance node at the output easing system integration. SAR ADCs are becoming popular at lower technologies as they are based on device switching rather than amplifying circuits. But recent SAR ADCs that have good energy efficiency have had relatively large input capacitance increasing the driver power. We present a 2X time interleaved (TI) SAR ADC which has the lowest input capacitance of 133fF in literature. The sampling capacitor is separated from the capacitive digital to analog converter (DAC) array by performing the input and DAC reference subtraction in the current domain rather than as done traditionally in charge domain. The proposed ADC is fabricated in TSMC's 65nm general purpose process and occupies an area of 0.0338 mm^2. The measured ADC spurious free dynamic range (SFDR) is 57dB and the measured effective number of bits (ENOB) at nyquist rate is 7.55 bit while using 1.55mW power from 1 V supply. A sub 1V reference circuit is proposed, that exploits the complementary to absolute temperature (CTAT) and proportional to absolute temperature (PTAT) voltages in the beta multiplier circuit to attain a stable voltage with temperature and power supply. A one-time calibration is integrated in the architecture to get a good performance over process. Chopper stabilization is employed to reduce the flicker noise of the reference circuit. The prototype was simulated in TSMC 65nm process and we obtain the nominal output of 236mW, while consuming 0.7mW from power supply. Simulations show a temperature coefficient of 18 ppmC from -40 to 100C and with a power supply ranging from 0.8 to 2V

Operational transconductance amplifier with a rail-to-rail constant transconductance input stage.

Chan Shek-Hang.Thesis (M.Phil.)--Chinese University of Hong Kong, 2002.Includes bibliographical references (leaves 94-97).Abstracts in English and Chinese.Abstract --- p.iAcknowledgement --- p.ivTable of Contents --- p.vList of Figures --- p.ixList of Tables --- p.xiiiChapter Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Overview --- p.1Chapter 1.2 --- Significance of the research --- p.2Chapter 1.3 --- Objectives --- p.3Chapter 1.4 --- Thesis outline --- p.4Chapter Chapter 2 --- Background theory --- p.5Chapter 2.1 --- Introduction --- p.5Chapter 2.2 --- Electrical properties of MOS transistors --- p.5Chapter 2.2.1 --- Strong inversion --- p.5Chapter 2.2.2 --- Weak inversion --- p.6Chapter 2.2.3 --- Moderate inversion --- p.8Chapter 2.2.4 --- The transistors biased in this work --- p.8Chapter 2.3 --- Rail-to-rail signals --- p.8Chapter 2.4 --- Rail-to-rail operational amplifier --- p.10Chapter 2.4.1 --- Rail-to-rail differential input pairs --- p.10Chapter 2.4.1.1 --- Principle --- p.10Chapter 2.4.1.2 --- Two stage operational amplifier --- p.13Chapter 2.4.2 --- Folded-cascode gain stage --- p.14Chapter 2.5 --- The nature of operational amplifier distortion --- p.16Chapter 2.5.1 --- The total harmonic distortion --- p.17Chapter Chapter 3 --- Constant transconductance rail-to-rail input stage --- p.20Chapter 3.1 --- Introduction --- p.20Chapter 3.2 --- Review of constant-gm input stage --- p.20Chapter 3.2.1 --- Rail-to-rail input stages with current-based gm control --- p.20Chapter 3.2.1.1 --- gm controlled by three-times current mirror --- p.21Chapter 3.2.1.2 --- gm controlled by square root current control --- p.23Chapter 3.2.1.3 --- gm controlled by using current switches only --- p.25Chapter 3.2.2 --- Rail-to-rail input stages with voltage-based gm control --- p.28Chapter 3.2.2.1 --- gm controlled by an ideal zener diode --- p.28Chapter 3.2.2.2 --- gm controlled by two diodes --- p.30Chapter 3.2.2.3 --- gm controlled by an electronic zener --- p.31Chapter 3.3 --- Conclusion --- p.32Chapter Chapter 4 --- Proposed constant transconductance rail-to-rail input stage --- p.34Chapter 4.1 --- Introduction --- p.34Chapter 4.2 --- Principle of the conventional input stage --- p.35Chapter 4.2.1 --- Translinear circuit --- p.35Chapter 4.3 --- Previous work --- p.36Chapter 4.3.1 --- Input bias circuit --- p.36Chapter 4.3.2 --- Weak inversion operation --- p.38Chapter 4.3.3 --- Power up problem --- p.43Chapter 4.4 --- Operational transconductance amplifier with proposed input biased stage --- p.47Chapter 4.4.1 --- Proposed input biased stage architecture --- p.47Chapter 4.4.2 --- Proposed input biased stage with 2 gm control circuits --- p.50Chapter 4.4.3 --- OTA with proposed input biased stage --- p.51Chapter Chapter 5 --- Simulation Results --- p.54Chapter 5.1 --- Introduction --- p.54Chapter 5.2 --- DC bias simulation --- p.54Chapter 5.2.1 --- Total transconductance variation --- p.54Chapter 5.2.2 --- Power consumption --- p.56Chapter 5.3 --- AC simulation --- p.56Chapter 5.3.1 --- Open-loop gain --- p.57Chapter 5.3.2 --- Gain-bandwidth product --- p.59Chapter 5.3.3 --- Phase margin --- p.59Chapter 5.4 --- Transient simulation --- p.60Chapter 5.4.1 --- Voltage follower --- p.60Chapter 5.4.2 --- Total harmonic distortion --- p.62Chapter 5.4.3 --- Step response --- p.65Chapter 5.5 --- Conclusion --- p.67Chapter Chapter 6 --- Layout Consideration --- p.68Chapter 6.1 --- Introduction --- p.68Chapter 6.2 --- Substrate tap --- p.68Chapter 6.3 --- Input protection circuitry --- p.69Chapter 6.4 --- Die micrographs of the OTA --- p.71Chapter Chapter 7 --- Measurement Results --- p.74Chapter 7.1 --- Introduction --- p.74Chapter 7.2 --- DC bias measurement results --- p.74Chapter 7.2.1 --- Total transconductance variation --- p.74Chapter 7.2.2 --- Power consumption --- p.77Chapter 7.3 --- AC measurement results --- p.78Chapter 7.3.1 --- Open-loop gain --- p.78Chapter 7.3.2 --- Gain-bandwidth product --- p.81Chapter 7.3.3 --- Phase margin --- p.81Chapter 7.4 --- Transient measurement result --- p.82Chapter 7.4.1 --- Voltage follower --- p.82Chapter 7.4.2 --- Total harmonic distortion --- p.85Chapter 7.4.3 --- Step response --- p.87Chapter 7.5 --- Conclusion --- p.88Chapter Chapter 8 --- Conclusion --- p.90Chapter 8.1 --- Contribution --- p.90Chapter 8.2 --- Further development --- p.91Chapter Chapter 9 --- Appendix --- p.92Chapter Chapter 10 --- Bibliography --- p.9

ダイナミック・アナログ回路を用いる高精度AD変換器の設計技術に関する研究

東京都市大学2018年度（平成30年

Analog Front-End Circuits for Massive Parallel 3-D Neural Microsystems.

Understanding dynamics of the brain has tremendously improved due to the progress in neural recording techniques over the past five decades. The number of simultaneously recorded channels has actually doubled every 7 years, which implies that a recording system with a few thousand channels should be available in the next two decades. Nonetheless, a leap in the number of simultaneous channels has remained an unmet need due to many limitations, especially in the front-end recording integrated circuits (IC). This research has focused on increasing the number of simultaneously recorded channels and providing modular design approaches to improve the integration and expansion of 3-D recording microsystems. Three analog front-ends (AFE) have been developed using extremely low-power and small-area circuit techniques on both the circuit and system levels. The three prototypes have investigated some critical circuit challenges in power, area, interface, and modularity. The first AFE (16-channels) has optimized energy efficiency using techniques such as moderate inversion, minimized asynchronous interface for data acquisition, power-scalable sampling operation, and a wide configuration range of gain and bandwidth. Circuits in this part were designed in a 0.25μm CMOS process using a 0.9-V single supply and feature a power consumption of 4μW/channel and an energy-area efficiency of 7.51x10^15 in units of J^-1Vrms^-1mm^-2. The second AFE (128-channels) provides the next level of scaling using dc-coupled analog compression techniques to reject the electrode offset and reduce the implementation area further. Signal processing techniques were also explored to transfer some computational power outside the brain. Circuits in this part were designed in a 180nm CMOS process using a 0.5-V single supply and feature a power consumption of 2.5μW/channel, and energy-area efficiency of 30.2x10^15 J^-1Vrms^-1mm^-2. The last AFE (128-channels) shows another leap in neural recording using monolithic integration of recording circuits on the shanks of neural probes. Monolithic integration may be the most effective approach to allow simultaneous recording of more than 1,024 channels. The probe and circuits in this part were designed in a 150 nm SOI CMOS process using a 0.5-V single supply and feature a power consumption of only 1.4μW/channel and energy-area efficiency of 36.4x10^15 J^-1Vrms^-1mm^-2.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/98070/1/ashmouny_1.pd

Low-Power Low-Noise CMOS Analog and Mixed-Signal Design towards Epileptic Seizure Detection

About 50 million people worldwide suffer from epilepsy and one third of them have seizures that are refractory to medication. In the past few decades, deep brain stimulation (DBS) has been explored by researchers and physicians as a promising way to control and treat epileptic seizures. To make the DBS therapy more efficient and effective, the feedback loop for titrating therapy is required. It means the implantable DBS devices should be smart enough to sense the brain signals and then adjust the stimulation parameters adaptively. This research proposes a signal-sensing channel configurable to various neural applications, which is a vital part for a future closed-loop epileptic seizure stimulation system. This doctoral study has two main contributions, 1) a micropower low-noise neural front-end circuit, and 2) a low-power configurable neural recording system for both neural action-potential (AP) and fast-ripple (FR) signals. The neural front end consists of a preamplifier followed by a bandpass filter (BPF). This design focuses on improving the noise-power efficiency of the preamplifier and the power/pole merit of the BPF at ultra-low power consumption. In measurement, the preamplifier exhibits 39.6-dB DC gain, 0.8 Hz to 5.2 kHz of bandwidth (BW), 5.86-μVrms input-referred noise in AP mode, while showing 39.4-dB DC gain, 0.36 Hz to 1.3 kHz of BW, 3.07-μVrms noise in FR mode. The preamplifier achieves noise efficiency factor (NEF) of 2.93 and 3.09 for AP and FR modes, respectively. The preamplifier power consumption is 2.4 μW from 2.8 V for both modes. The 6th-order follow-the-leader feedback elliptic BPF passes FR signals and provides -110 dB/decade attenuation to out-of-band interferers. It consumes 2.1 μW from 2.8 V (or 0.35 μW/pole) and is one of the most power-efficient high-order active filters reported to date. The complete front-end circuit achieves a mid-band gain of 38.5 dB, a BW from 250 to 486 Hz, and a total input-referred noise of 2.48 μVrms while consuming 4.5 μW from the 2.8 V power supply. The front-end NEF achieved is 7.6. The power efficiency of the complete front-end is 0.75 μW/pole. The chip is implemented in a standard 0.6-μm CMOS process with a die area of 0.45 mm^2. The neural recording system incorporates the front-end circuit and a sigma-delta analog-to-digital converter (ADC). The ADC has scalable BW and power consumption for digitizing both AP and FR signals captured by the front end. Various design techniques are applied to the improvement of power and area efficiency for the ADC. At 77-dB dynamic range (DR), the ADC has a peak SNR and SNDR of 75.9 dB and 67 dB, respectively, while consuming 2.75-mW power in AP mode. It achieves 78-dB DR, 76.2-dB peak SNR, 73.2-dB peak SNDR, and 588-μW power consumption in FR mode. Both analog and digital power supply voltages are 2.8 V. The chip is fabricated in a standard 0.6-μm CMOS process. The die size is 11.25 mm^2. The proposed circuits can be extended to a multi-channel system, with the ADC shared by all channels, as the sensing part of a future closed-loop DBS system for the treatment of intractable epilepsy