A dynamically reconfigurable pattern matcher for regular expressions on FPGA

In this article we describe how to expand a partially dynamic reconfig- urable pattern matcher for regular expressions presented in previous work by Di- vyasree and Rajashekar [2]. The resulting, extended, pattern matcher is fully dynamically reconfigurable. First, the design is adapted for use with parameterisable configurations, a method for Dynamic Circuit Specialization. Using parameteris- able configurations allows us to achieve the same area gains as the hand crafted reconfigurable design, with the benefit that parameterisable configurations can be applied automatically. This results in a design that is more easily adaptable to spe- cific applications and allows for an easier design exploration. Additionally, the pa- rameterisable configuration implementation is also generated automatically, which greatly reduces the design overhead of using dynamic reconfiguration. Secondly, we propose a number of expansions to the original design to overcome several limitations in the original design that constrain the dynamic reconfigurability of the pattern matcher. We propose two different solutions to dynamically change the character that is matched in a certain block. The resulting pattern matcher, after these changes, is fully dynamically reconfigurable, all aspects of the implemented regular expression can be changed at run-time

Parallel data compression

Data compression schemes remove data redundancy in communicated and stored data and increase the effective capacities of communication and storage devices. Parallel algorithms and implementations for textual data compression are surveyed. Related concepts from parallel computation and information theory are briefly discussed. Static and dynamic methods for codeword construction and transmission on various models of parallel computation are described. Included are parallel methods which boost system speed by coding data concurrently, and approaches which employ multiple compression techniques to improve compression ratios. Theoretical and empirical comparisons are reported and areas for future research are suggested

Design And Implementation Of A Hardware Level Content Networking Front End Device

The bandwidth and speed of network connections are continually increasing. The speed increase in network technology is set to soon outpace the speed increase in CMOS technology. This asymmetrical growth is beginning to causing software applications that once worked with then current levels of network traffic to flounder under the new high data rates. Processes that were once executed in software now have to be executed, partially if not wholly in hardware. One such application that could benefit from hardware implementation is high layer routing. By allowing a network device to peer into higher layers of the OSI model, the device can scan for viruses, provide higher quality-of-service (QoS), and efficiently route packets. This thesis proposes an architecture for a device that will utilize hardware-level string matching to distribute incoming requests for a server farm. The proposed architecture is implemented in VHDL, synthesized, and laid out on an Altera FPGA

Gbit/second lossless data compression hardware

This thesis investigates how to improve the performance of lossless data compression hardware as a tool to reduce the cost per bit stored in a computer system or transmitted over a communication network. Lossless data compression allows the exact reconstruction of the original data after decompression. Its deployment in some high-bandwidth applications has been hampered due to performance limitations in the compressing hardware that needs to match the performance of the original system to avoid becoming a bottleneck. Advancing the area of lossless data compression hardware, hence, offers a valid motivation with the potential of doubling the performance of the system that incorporates it with minimum investment. This work starts by presenting an analysis of current compression methods with the objective of identifying the factors that limit performance and also the factors that increase it. [Continues.

Design techniques for low-power wide-band direct digital frequency synthesizers of spread spectrum communication applications

For frequency agile communication systems, fast frequency switching in fine frequency steps with good spectral purity is crucial. Direct Digital Frequency Synthesizer (DDFS) is best suitable for these applications, but is not widely employed in wireless communication systems due to its high power consumption. In general, low power and high integration design are two challenges for mixed signal-circuits and communication systems designers. In this dissertation, new design techniques for DDFS at both architecture and circuit levels are proposed and investigated in order to minimize power consumption and optimize performance. A ROM-less low power wide band DDFS prototype using segmented sine wave Digital-to-Analog Converter (DAC) were designed, fabricated and tested to demonstrate the new design techniques.;First, to further reduce power consumption and save chip area, two new phase interpolation ROM less DDFS architectures are proposed. Segmentation technique is applied to the design of sine wave DAC for DDFS: (1) based upon trigonometric identities, a segmented sine wave DAC with fine nonlinear interpolation DAC\u27s is proposed; (2) based upon first order Taylor series and simple linear interpolation, a segmented sine wave DAC with a fine linear interpolation DAC is proposed. Second, a figure of merit (FM) is defined to find the optimal sine wave DAC segmentations for various resolutions of the segmented sine wave DAC\u27s. The device mismatch effects on the performance of segmented sine wave were also discussed. Third, For DDFS using current-steering segmented sine wave DAC with 12-b phase resolution and 11-b amplitude resolution, a behavioral model in Verilog was used to verify the functionality and validate the architecture. Finally, a DDFS prototype was designed and fabricated in a standard 0.25mum CMOS process. The measured SFDR is better than 50 dB with output frequencies up to 3/8 of the 300 MHz clock frequency. The prototype occupies an active area of 1.4 mm2 and consumes 240 mW for 300 MHz clock frequency. The new techniques reduce the power dissipation and die area substantially when compared to conventional ROM based DDFS designs with on-chip DAC

A retrieval-based dialogue system utilizing utterance and context embeddings

Finding semantically rich and computer-understandable representations for textual dialogues, utterances and words is crucial for dialogue systems (or conversational agents), as their performance mostly depends on understanding the context of conversations. Recent research aims at finding distributed vector representations (embeddings) for words, such that semantically similar words are relatively close within the vector-space. Encoding the "meaning" of text into vectors is a current trend, and text can range from words, phrases and documents to actual human-to-human conversations. In recent research approaches, responses have been generated utilizing a decoder architecture, given the vector representation of the current conversation. In this paper, the utilization of embeddings for answer retrieval is explored by using Locality-Sensitive Hashing Forest (LSH Forest), an Approximate Nearest Neighbor (ANN) model, to find similar conversations in a corpus and rank possible candidates. Experimental results on the well-known Ubuntu Corpus (in English) and a customer service chat dataset (in Dutch) show that, in combination with a candidate selection method, retrieval-based approaches outperform generative ones and reveal promising future research directions towards the usability of such a system.Comment: A shorter version is accepted at ICMLA2017 conference; acknowledgement added; typos correcte

Practical Variation-Aware Designs in Quantum Computing

Variations are prevalent in all aspects of quantum computing. On solid state quantum devices, fabrication errors lead to variations in device connectivity. Among the qubits that are available for use, there are still variations in multiple properties. Other than hardware variations, different algorithms and operations impose different requirements on the devices and systems. In order to bridge the gap between the theory and implementation of quantum computing, we need practical designs that are aware of variations and system-level tradeoffs. This thesis includes three examples of adapting to variations: choosing two-qubit basis gates based on individual qubits’ properties, adapting error correction codes and using modular architecture to support fault-tolerant computation in the presence of fabrication defects, and adapting real time decoding protocols to support large patches of topological codes that arise during lattice surgery operations