Multi-band OFDM UWB receiver with narrowband interference suppression

A multi band orthogonal frequency division multiplexing (MB-OFDM) compatible ultra wideband (UWB) receiver with narrowband interference (NBI) suppression capability is presented. The average transmit power of UWB system is limited to -41.3 dBm/MHz in order to not interfere existing narrowband systems. Moreover, it must operate even in the presence of unintentional radiation of FCC Class-B compatible devices. If this unintentional radiation resides in the UWB band, it can jam the communication. Since removing the interference in digital domain requires higher dynamic range of analog front-end than removing it in analog domain, a programmable analog notch filter is used to relax the receiver requirements in the presence of NBI. The baseband filter is placed before the variable gain amplifier (VGA) in order to reduce the signal swing at the VGA input. The frequency hopping period of MB-OFDM puts a lower limit on the settling time of the filter, which is inverse proportional to notch bandwidth. However, notch bandwidth should be low enough not to attenuate the adjacent OFDM tones. Since these requirements are contradictory, optimization is needed to maximize overall performance. Two different NBI suppression schemes are tested. In the first scheme, the notch filter is operating for all sub-bands. In the second scheme, the notch filter is turned on during the sub-band affected by NBI. Simulation results indicate that the UWB system with the first and the second suppression schemes can handle up to 6 dB and 14 dB more NBI power, respectively. The results of this work are not limited to MB-OFDM UWB system, and can be applied to other frequency hopping systems

Radio-Communications Architectures

Wireless communications, i.e. radio-communications, are widely used for our different daily needs. Examples are numerous and standard names like BLUETOOTH, WiFI, WiMAX, UMTS, GSM and, more recently, LTE are well-known [Baudoin et al. 2007]. General applications in the RFID or UWB contexts are the subject of many papers. This chapter presents radio-frequency (RF) communication systems architecture for mobile, wireless local area networks (WLAN) and connectivity terminals. An important aspect of today's applications is the data rate increase, especially in connectivity standards like WiFI and WiMAX, because the user demands high Quality of Service (QoS). To increase the data rate we tend to use wideband or multi-standard architecture. The concept of software radio includes a self-reconfigurable radio link and is described here on its RF aspects. The term multi-radio is preferred. This chapter focuses on the transmitter, yet some considerations about the receiver are given. An important aspect of the architecture is that a transceiver is built with respect to the radio-communications signals. We classify them in section 2 by differentiating Continuous Wave (CW) and Impulse Radio (IR) systems. Section 3 is the technical background one has to consider for actual applications. Section 4 summarizes state-of-the-art high data rate architectures and the latest research in multi-radio systems. In section 5, IR architectures for Ultra Wide Band (UWB) systems complete this overview; we will also underline the coexistence and compatibility challenges between CW and IR systems

System-level design and RF front-end implementation for a 3-10ghz multiband-ofdm ultrawideband receiver and built-in testing techniques for analog and rf integrated circuits

This work consists of two main parts: a) Design of a 3-10GHz UltraWideBand (UWB) Receiver and b) Built-In Testing Techniques (BIT) for Analog and RF circuits. The MultiBand OFDM (MB-OFDM) proposal for UWB communications has received significant attention for the implementation of very high data rate (up to 480Mb/s) wireless devices. A wideband LNA with a tunable notch filter, a downconversion quadrature mixer, and the overall radio system-level design are proposed for an 11-band 3.4-10.3GHz direct conversion receiver for MB-OFDM UWB implemented in a 0.25mm BiCMOS process. The packaged IC includes an RF front-end with interference rejection at 5.25GHz, a frequency synthesizer generating 11 carrier tones in quadrature with fast hopping, and a linear phase baseband section with 42dB of gain programmability. The receiver IC mounted on a FR-4 substrate provides a maximum gain of 67-78dB and NF of 5-10dB across all bands while consuming 114mA from a 2.5V supply. Two BIT techniques for analog and RF circuits are developed. The goal is to reduce the test cost by reducing the use of analog instrumentation. An integrated frequency response characterization system with a digital interface is proposed to test the magnitude and phase responses at different nodes of an analog circuit. A complete prototype in CMOS 0.35mm technology employs only 0.3mm2 of area. Its operation is demonstrated by performing frequency response measurements in a range of 1 to 130MHz on 2 analog filters integrated on the same chip. A very compact CMOS RF RMS Detector and a methodology for its use in the built-in measurement of the gain and 1dB compression point of RF circuits are proposed to address the problem of on-chip testing at RF frequencies. The proposed device generates a DC voltage proportional to the RMS voltage amplitude of an RF signal. A design in CMOS 0.35mm technology presents and input capacitance <15fF and occupies and area of 0.03mm2. The application of these two techniques in combination with a loop-back test architecture significantly enhances the testability of a wireless transceiver system

Analysis and design of low power CMOS ultra wideband receiver

This research concentrates on the design and analysis of low power ultra wideband receivers for Multiband Orthogonal Frequency Division Multiplexing systems. Low power design entails different performance tradeoffs, which are analyzed. Relationship among power consumption, achievable noise figure and linearity performance including distortion products (cross-modulation, inter-modulation and harmonic distortion) are derived. From these relationships, circuit design proceeds with allocation of gain among different sub circuit blocks for power optimum system. A power optimum RF receiver front-end for MB-OFDM based UWB systems is designed that covers all the MB-OFDM spectrum between 3.1 GHZ to 9.6 GHZ. The receiver consists of a low-noise amplifier, down-converter, channel select filter and programmable gain amplifier and occupies only 1mm 2 in 0.13um CMOS process. Receiver consumes 20 mA from a 1.2 V supply and has the measured gain of 69db, noise figure less than 6 dB and input IIP 3 of -6 dBm

Design Of Receiver Lowpass Filter For UWB Application Using 0.18μm Cmos Technology

The design and analysis of a baseband lowpass filter for UWB application in front end receiver is presented in this report. The objective of this project is to design a lowpass filter which operates with voltage 1.80V and has a bandwidth 264.00MHz by using Silterra 0.18um SMCMOS technology. Transconductor-capacitor filter is the filter architecture being chosen to design and analysis the lowpass filter due to its capability to operate in high frequency, but low power and low cost as compared to passive filter. First to fourth order Gm-C Butterworth lowpass filter is designed and their performance is compared to allow effective filter order selection. First order Gm-C Butterworth lowpass filter has bandwidth 264.00MHz and DC gain of -0.25dB. The 1dB compression point of first order filter is 3.68dBm and third order intercepts point (IP3) at 11.69dBm. The power consumption of first order filter is 5.00mW. Second order filter has bandwidth of 264.00Mhz, DC gain of -0.13dB, 1dB compression point at -0.64dBm, IP3 at 6.05dBm and power consumption of 10.01mW. The third order Gm-C filter has bandwidth 264.00MHz, DC gain of -0.38dB, 1dB compression point at -0.077dBm IP3 at 6.61dBm, power consumption of 15.02mW. The forth order Gm-C filter has bandwidth 264.00MHz, DC gain of -0.26dB, 1dB compression point at -1.92dBm IP3 at 4.50dBm, power consumption of 20.02mW. Third order Gm-C Butterworth lowpass filter has been chosen as baseband filter due to its sharper rolloff in transition from passband to stopband than first and second order filter, and has a better linearity than fourth order filter. The third order filter consists of 72 transistors and 3 MIM capacitor. The size of layout of third order Gm-C filter is 294 286 μm× μm . The designed filter will be sent to Silterra for fabrication into chip and furthermore chip characterization and measurement will be carried out to make sure the measurement of real filter chip can match well as closed as to the simulated result of filter design

Multi-band OFDM UWB receiver with narrowband interference suppression

A multi band orthogonal frequency division multiplexing (MB-OFDM) compatible ultra wideband (UWB) receiver with narrowband interference (NBI) suppression capability is presented. The average transmit power of UWB system is limited to -41.3 dBm/MHz in order to not interfere existing narrowband systems. Moreover, it must operate even in the presence of unintentional radiation of FCC Class-B compatible devices. If this unintentional radiation resides in the UWB band, it can jam the communication. Since removing the interference in digital domain requires higher dynamic range of analog front-end than removing it in analog domain, a programmable analog notch filter is used to relax the receiver requirements in the presence of NBI. The baseband filter is placed before the variable gain amplifier (VGA) in order to reduce the signal swing at the VGA input. The frequency hopping period of MB-OFDM puts a lower limit on the settling time of the filter, which is inverse proportional to notch bandwidth. However, notch bandwidth should be low enough not to attenuate the adjacent OFDM tones. Since these requirements are contradictory, optimization is needed to maximize overall performance. Two different NBI suppression schemes are tested. In the first scheme, the notch filter is operating for all sub-bands. In the second scheme, the notch filter is turned on during the sub-band affected by NBI. Simulation results indicate that the UWB system with the first and the second suppression schemes can handle up to 6 dB and 14 dB more NBI power, respectively. The results of this work are not limited to MB-OFDM UWB system, and can be applied to other frequency hopping systems

Continuous-time low-pass filters for integrated wideband radio receivers

This thesis concentrates on the design and implementation of analog baseband continuous-time low-pass filters for integrated wideband radio receivers. A total of five experimental analog baseband low-pass filter circuits were designed and implemented as a part of five single-chip radio receivers in this work. After the motivation for the research work presented in this thesis has been introduced, an overview of analog baseband filters in radio receivers is given first. In addition, a review of the three receiver architectures and the three wireless applications that are adopted in the experimental work of this thesis is presented. The relationship between the integrator non-idealities and integrator Q-factor, as well as the effect of the integrator Q-factor on the filter frequency response, are thoroughly studied on the basis of a literature review. The theoretical study that is provided is essential for the gm-C filter synthesis with non-ideal lossy integrators that is presented after the introduction of different techniques to realize integrator-based continuous-time low-pass filters. The filter design approach proposed for gm-C filters is original work and one of the main points in this thesis, in addition to the experimental IC implementations. Two evolution versions of fourth-order 10-MHz opamp-RC low-pass filters designed and implemented for two multicarrier WCDMA base-station receivers in a 0.25-µm SiGe BiCMOS technology are presented, along with the experimental results of both the low-pass filters and the corresponding radio receivers. The circuit techniques that were used in the three gm-C filter implementations of this work are described and a common-mode induced even-order distortion in a pseudo-differential filter is analyzed. Two evolution versions of fifth-order 240-MHz gm-C low-pass filters that were designed and implemented for two single-chip WiMedia UWB direct-conversion receivers in a standard 0.13-µm and 65-nm CMOS technology, respectively, are presented, along with the experimental results of both the low-pass filters and the second receiver version. The second UWB filter design was also embedded with an ADC into the baseband of a 60-GHz 65-nm CMOS radio receiver. In addition, a third-order 1-GHz gm-C low-pass filter was designed, rather as a test structure, for the same receiver. The experimental results of the receiver and the third gm-C filter implementation are presented

Advances in Integrated Circuit Design and Implementation for New Generation of Wireless Transceivers

User’s everyday outgrowing demand for high-data and high performance mobile devices pushes industry and researchers into more sophisticated systems to fulfill those expectations. Besides new modulation techniques and new system designs, significant improvement is required in the transceiver building blocks to handle higher data rates with reasonable power efficiency. In this research the challenges and solution to improve the performance of wireless communication transceivers is addressed. The building block that determines the efficiency and battery life of the entire mobile handset is the power amplifier. Modulations with large peak to average power ratio severely degrade efficiency in the conventional fixed-biased power amplifiers (PAs). To address this challenge, a novel PA is proposed with an adaptive load for the PA to improve efficiency. A nonlinearity cancellation technique is also proposed to improve linearity of the PA to satisfy the EVM and ACLR specifications. Ultra wide-band (UWB) systems are attractive due to their ability for high data rate, and low power consumption. In spite of the limitation assigned by the FCC, the coexistence of UWB and NB systems are still an unsolved challenge. One of the systems that is majorly affected by the UWB signal, is the 802.11a system (5 GHz Wi-Fi). A new analog solution is proposed to minimize the interference level caused by the impulse Radio UWB transmitter to nearby narrowband receivers. An efficient 400 Mpulse/s IR-UWB transmitter is implemented that generates an analog UWB pulse with in-band notch that covers the majority of the UWB spectrum. The challenge in receiver (RX) design is the over increasing out of blockers in applications such as cognitive and software defined radios, which are required to tolerate stronger out-of-band (OB) blockers. A novel RX is proposed with a shunt N-path high-Q filter at the LNA input to attenuate OB-blockers. To further improve the linearity, a novel baseband blocker filtering techniques is proposed. A new TIA has been designed to maintain the good linearity performance for blockers at large frequency offsets. As a result, a +22 dBm IIP3 with 3.5 dB NF is achieved. Another challenge in the RX design is the tough NF and linearity requirements for high performance systems such as carrier aggregation. To improve the NF, an extra gain stage is added after the LNA. An N-path high-Q band-pass filter is employed at the LNA output together with baseband blocker filtering technique to attenuate out-of-band blockers and improve the linearity. A noise-cancellation technique based on the frequency translation has been employed to improve the NF. As a result, a 1.8dB NF with +5 dBm IIP3 is achieved. In addition, a new approach has been proposed to reject out of band blockers in carrier aggregation scenarios. The proposed solution also provides carrier to carrier isolation compared to typical solution for carrier aggregation

System design and validation of multi-band OFDM wireless communications with multiple antennas

[no abstract

A digital polar transmitter for multi-band OFDM Ultra-WideBand

Linear power amplifiers used to implement the Ultra-Wideband standard must be backed off from optimum power efficiency to meet the standard specifications and the power efficiency suffers. The problem of low efficiency can be mitigated by polar modulation. Digital polar architectures have been employed on numerous wireless standards like GSM, EDGE, and WLAN, where the fractional bandwidths achieved are only about 1%, and the power levels achieved are often in the vicinity of 20 dBm. Can the architecture be employed on wireless standards with low-power and high fractional bandwidth requirements and yet achieve good power efficiency? To answer these question, this thesis studies the application of a digital polar transmitter architecture with parallel amplifier stages for UWB. The concept of the digital transmitter is motivated and inspired by three factors. First, unrelenting advances in the CMOS technology in deep-submicron process and the prevalence of low-cost Digital Signal processing have resulted in the realization of higher level of integration using digitally intensive approaches. Furthermore, the architecture is an evolution of polar modulation, which is known for high power efficiency in other wireless applications. Finally, the architecture is operated as a digital-to-analog converter which circumvents the use of converters in conventional transmitters. Modeling and simulation of the system architecture is performed on the Agilent Advanced Design System Ptolemy simulation platform. First, by studying the envelope signal, we found that envelope clipping results in a reduction in the peak-to-average power ratio which in turn improves the error vector magnitude performance (figure of merit for the study). In addition, we have demonstrated that a resolution of three bits suffices for the digital polar transmitter when envelope clipping is performed. Next, this thesis covers a theoretical derivation for the estimate of the error vector magnitude based on the resolution, quantization and phase noise errors. An analysis on the process variations - which result in gain and delay mismatches - for a digital transmitter architecture with four bits ensues. The above studies allow RF designers to estimate the number of bits required and the amount of distortion that can be tolerated in the system. Next, a study on the circuit implementation was conducted. A DPA that comprises 7 parallel RF amplifiers driven by a constant RF phase-modulated signal and 7 cascode transistors (individually connected in series with the bottom amplifiers) digitally controlled by a 3-bit digitized envelope signal to reconstruct the UWB signal at the output. Through the use of NFET models from the IBM 130-nm technology, our simulation reveals that our DPA is able to achieve an EVM of - 22 dB. The DPA simulations have been performed at 3.432 GHz centre frequency with a channel bandwidth of 528 MHz, which translates to a fractional bandwidth of 15.4%. Drain efficiencies of 13.2/19.5/21.0% have been obtained while delivering -1.9/2.5/5.5 dBm of output power and consuming 5/9/17 mW of power. In addition, we performed a yield analysis on the digital polar amplifier, based on unit-weighted and binary-weighted architecture, when gain variations are introduced in all the individual stages. The dynamic element matching method is also introduced for the unit-weighted digital polar transmitter. Monte Carlo simulations reveal that when the gain of the amplifiers are allowed to vary at a mean of 1 with a standard deviation of 0.2, the binary-weighted architecture obtained a yield of 79%, while the yields of the unit-weighted architectures are in the neighbourhood of 95%. Moreover, the dynamic element matching technique demonstrates an improvement in the yield by approximately 3%. Finally, a hardware implementation for this architecture based on software-defined arbitrary waveform generators is studied. In this section, we demonstrate that the error vector magnitude results obtained with a four-stage binary-weighted digital polar transmitter under ideal combining conditions fulfill the European Computer Manufacturers Association requirements. The proposed experimental setup, believed to be the first ever attempted, confirm the feasibility of a digital polar transmitter architecture for Ultra-Wideband. In addition, we propose a number of power combining techniques suitable for the hardware implementation. Spatial power combining, in particular, shows a high potential for the digital polar transmitter architecture. The above studies demonstrate the feasibility of the digital polar architecture with good power efficiency for a wideband wireless standard with low-power and high fractional bandwidth requirements