A design for testability study on a high performance automatic gain control circuit.

A comprehensive testability study on a commercial automatic gain control circuit is presented which aims to identify design for testability (DfT) modifications to both reduce production test cost and improve test quality. A fault simulation strategy based on layout extracted faults has been used to support the study. The paper proposes a number of DfT modifications at the layout, schematic and system levels together with testability. Guidelines that may well have generic applicability. Proposals for using the modifications to achieve partial self test are made and estimates of achieved fault coverage and quality levels presente

A 16 channel high-voltage driver with 14 bit resolution for driving piezoelectric actuators

A high-voltage, 16 channel driver with a maximum voltage of 72 volt and 14 bit resolution in a high-voltage CMOS (HV-CMOS) process is presented. This design incorporates a 14 bit monotonic by design DAC together with a high-voltage complementary class AB output stage for each channel. All 16 channels are used for driving a piezoelectric actuator within the control loop of a micropositioning system. Since the output voltages are static most of the time, a class AB amplifier is used, implementing voltage feedback to achieve 14 bit accuracy. The output driver consists of a push-pull stage with a built-in output current limitation and high-impedance mode. Also a protection circuit is added which limits the internal current when the output voltage saturates against the high-voltage rail. The 14 bit resolution of each channel is generated with a segmented resistor string DAC which assures monotonic by design behavior by using leapfrogging of the buffers used between segments. A diagonal shuffle layout is used for the resistor strings leading to cancellation of first order process gradients. The dense integration of 16 channels with high peak currents results in crosstalk, countered in this design by using staggered switching and resampling of the output voltages

Low power data converters for specific applications

Due to increasing importance of portable equipment and reduction of the supply voltage due to technology scaling, recent efforts in the design of mixed-signal circuits have focused on developing new techniques to reduce the power dissipation and supply voltage. This requires research into new architectures and circuit techniques that enable both integration and programmability. Programmability allows each component to be used for different applications, reducing the total number of components, and increased integration by eliminating external components will reduce cost and power;Since data converters are used in many different applications, in this thesis new low voltage and low power data converter techniques at both the architecture and circuit design levels are investigated to minimize power dissipation and supply voltage. To demonstrate the proposed techniques, test the performance of the proposed architectures, and verify their effectiveness in terms of power savings, five prototype chips are fabricated and tested;First, a re-configurable data converter (RDC) architecture is presented that can be programmed as analog-to-digital converter (ADC), digital-to-analog converter (DAC), or both. The reconfigurability of the RDC to different numbers of ADCs and DACs having different speeds and resolutions makes it an ideal choice for analog test bus, mixed-mode boundary scan, and built-in self test applications. It combines the advantages of both analog test buses and boundary scan techniques while the area overhead of the proposed techniques is very low compared to the mixed-mode boundary scan techniques. RDC can save power by allowing the designer to program it as the right converter for desired application. This architecture can be potentially implemented inside a field programmable gate array (FPGA) to allow the FPGA communicate with the analog world. It can also be used as a stand-alone product to give flexibility to the user to choose ADC/DAC combinations for the desired application;Next, a new method for designing low power and small area ROMless direct digital frequency synthesizers (DDFSs) is presented. In this method, a non-linear digital-to-analog converter is used to replace the phase-to-sine amplitude ROM look-up table and the linear DAC in conventional DDFS. Since the non-linear DAC converts the phase information directly into analog sine wave, no phase-to-amplitude ROM look-up table is required;Finally, a new low voltage technique based on biased inverting opamp that can have almost rail-to-rail swing with continuously valid output is discussed. Based on this biasing technique, a 10-bit segmented R-2R DAC and an 8-bit successive approximation ADC are designed and presented

High-Performance Bioinstrumentation for Real-Time Neuroelectrochemical Traumatic Brain Injury Monitoring

Traumatic brain injury (TBI) has been identified as an important cause of death and severe disability in all age groups and particularly in children and young adults. Central to TBIs devastation is a delayed secondary injury that occurs in 30–40% of TBI patients each year, while they are in the hospital Intensive Care Unit (ICU). Secondary injuries reduce survival rate after TBI and usually occur within 7 days post-injury. State-of-art monitoring of secondary brain injuries benefits from the acquisition of high-quality and time-aligned electrical data i.e., ElectroCorticoGraphy (ECoG) recorded by means of strip electrodes placed on the brains surface, and neurochemical data obtained via rapid sampling microdialysis and microfluidics-based biosensors measuring brain tissue levels of glucose, lactate and potassium. This article progresses the field of multi-modal monitoring of the injured human brain by presenting the design and realization of a new, compact, medical-grade amperometry, potentiometry and ECoG recording bioinstrumentation. Our combined TBI instrument enables the high-precision, real-time neuroelectrochemical monitoring of TBI patients, who have undergone craniotomy neurosurgery and are treated sedated in the ICU. Electrical and neurochemical test measurements are presented, confirming the high-performance of the reported TBI bioinstrumentation

A system-on-chip digital pH meter for use in a wireless diagnostic capsule

This paper describes the design and implementation of a system-on-chip digital pH meter, for use in a wireless capsule application. The system is organized around an 8-bit microcontroller, designed to be functionally identical to the Motorola 6805. The analog subsystem contains a floating-electrode ISFET, which is fully compatible with a commercial CMOS process. On-chip programmable voltage references and multiplexors permit flexibility with the minimum of external connections. The chip is designed in a modular fashion to facilitate verification and component re-use. The single-chip pH meter can be directly connected to a personal computer, and gives a response of 37 bits/pH, within an operating range of 7 pH units

A built-in self-test technique for high speed analog-to-digital converters

Fundação para a Ciência e a Tecnologia (FCT) - PhD grant (SFRH/BD/62568/2009

Precise linear signal generation with nonideal components and deterministic dynamic element matching

A dynamic element matching (DEM) approach to ADC testing is introduced. Two variants of this method are introduced and compared; a deterministic DEM method and a random DEM method. With both variants, a highly non-ideal DAC is used to generate an excitation for a DUT that has effective linearity that far exceeds that of the DAC. Simulation results show that both methods can be used for testing of ADCs. The deterministic DEM (DDEM) offers potential for a substantial reduction in the number of samples when compared with a random DEM approach with the same measurement accuracy. It is shown that the concept of usinf DEM for signal generation in a test environment finds applications well-beyond ADC testing. The DDEM approach offers potential for use in both production test and BIST environments

High-speed high-resolution low-power self-calibrated digital-to-analog converters

High-speed and high-resolution low-power digital-to-analog converters (DACs) are basic design blocks in many applications. Several obvious conflicting requirements such as high-speed, high-resolution, low-power, and small-area have to be satisfied. In this dissertation, a modular architecture for continuous self-calibrating DACs is proposed to satisfy the above requirements. This includes a redundant-cell-relay continuous self-calibration scheme. Several prototype DACs were implemented with self-calibration schemes. Also a DAC synthesis algorithm using a direct-mapping method and the modular structure was developed and implemented in the Cadence SKILL programming language.;One of the prototypes is a 250MS/s 8-bit continuous self-calibrated DAC that has been implemented in TSMC\u27s 0.25mu single poly five metal logic CMOS process. The structure of the self-calibrated current cell has high impedance and low sensitivity to output node voltage fluctuations. The chip has achieved +0.15/-0.1 LSB DNL, -0.6/+0.4 LSB INL, and 55dB SFDR with a lower input frequency at a conversion rate of 250MS/s. It consumes 8 mW of power in a 0.13 mm2 die area.;Glitches caused by switching of the calibration clock degrade the SFDR especially in high-speed applications. A new redundant-cell-relay continuous self-calibration scheme was proposed to reduce the glitches. Simulation results showed that the glitch energy is reduced 10 fold over existing schemes. A 10-bit DAC was implemented in the 0.25mu CMOS process mentioned above. +/-0.5 LSB INL and -0.45/+0.2 LSB DNL were measured and 70dB SFDR was achieved with a lower input frequency at a 250MS/s conversion rate. Up to the Nyquist rate, the SFDR is above 53dB at a conversion rate of 200MS/s. The DAC dissipates 8mW in a 0.3mm2 die area. The testing results verified the redundant-cell-relay continuous self-calibration for high-speed high-resolution low-power and low-cost DACs.;Additionally, a DAC synthesis algorithm was developed based on a direct mapping method. Given the specifications such as the DAC\u27s resolution, full range scale and technology, the synthesizer will map them directly into pre-existing functional blocks implemented in the DAC synthesis libraries. The program will then synthesize the schematic and layout that closely meet the given specifications

Fully digital-compatible built-in self-test solutions to linearity testing of embedded mixed-signal functions

Mixed-signal circuits, especially analog-to-digital and digital-to-analog converters, are the most widely used circuitry in electronic systems. In the most of the cases, mixed-signal circuits form the interface between the analog and digital worlds and enable the processing and recovering of the real-world information. Performance of mixed-signal circuits, such as linearity and noise, are then critical to any applications. Conventionally, mixed-signal circuits are tested by mixed-signal automatic test equipment (ATE). However, along with the continuous performance improvement, using conventionally methods increases test costs significantly since it takes much more time to test high-performance parts than low-performance ones and mixed-signal ATE testers could be extremely expensive depending on the test precision they provide. Another factor that makes mixed-signal testing more and more challenging is the advance of the integration level. In the popular system-on-chip applications, mixed-signal circuits are deeply embedded in the systems. With less observability and accessibility, conventionally external test methods can not guarantee the precision of the source signals and evaluations. Test performance is then degraded. This work investigates new methods using digital testers incorporated with on-chip, built-in self-test circuits to test the linearity performance of data converters with less test cost and better test performance. Digital testers are cheap to use since they only offer logic signals with direct connections. The analog sourcing and evaluation capabilities have to be absorbed by the on-chip BIST circuits, which, meanwhile, could benefit the test performance with access to the internal circuit nodes. The main challenge of the digital-compatible BIST methods is to implement the BIST circuits with enough high test performance but with low design complexity and cost. High-resolution data converter testing needs much higher-precision analog source signals and evaluation circuits. However, high-precision analog circuits are conventionally hard to design and costly, and their performance is subject to mismatch errors and process variations and cannot be guaranteed without careful testing. On the digital side, BIST circuits usually conduct procedure control and data processing. To make the BIST solution more universal, the control and processing performed by the digital BIST circuits should be simple and not rely on any complex microcontroller and DSP block. Therefore, the major tasks of this dissertation are 1) performance-robust analog BIST circuit design and 2) test procedure development. Analog BIST circuits in this work consist of only low-accuracy analog components, which are usually easy to design and cost effective. The precision is then obtained by applying the so-called deterministic dynamic element matching technique to the low-accuracy analog cells. The test procedure and data processing designed for the BIST system are simple and can be implemented by small logic circuits. In this dissertation, we discuss the proposed BIST solutions to ADC and DAC linearity testing in chapter 3 and chapter 5, respectively. In each case, the structure of the test system, the test procedure, and the theoretical analysis of the test performance are presented. Simulation results are shown to verify the efficacy of the methods. The ADC BIST system is also verified experimentally. In addition, chapter 4 introduces a system-identification based reduced-code testing method for pipeline ADCs. This method is able to reduce test time by more than 95%. And it is compatible with the proposed BIST method discussed in chapter 3

A graphical method for determining the uniqueness of operating points in self-biasing circuits

In self-biasing circuits, designers often use feedbacks to reduce the power-supply sensitivity and minimize the effects of process and temperature variations. Many self-stabilized circuits are used in SOC circuits even when the SOC has a small amount of AMS content. It is well-known that these self-stabilized circuits are vulnerable to not starting-up correctly so start-up circuits are often included to prevent the circuit from getting stuck in an undesired stable operating point. Determining the uniqueness of an operating point in a circuit is challenging since circuit simulators only give a single operating point rather than all operating points. Moreover, this problem is very closely related to the mathematical problem of finding all solutions to a set of nonlinear equations. Both the mathematical and computer science communities recognize this as an open problem with no solution in sight. In circuits with multiple operating points, when a circuit simulator always gives the desired operating point throughout the design and verification process, there is little evidence that one or more undesired operating points even exist. In the semiconductor industry, designers use experience and intuition to identify start-up problems. Some self-stabilized circuits designed by trusted engineers unpredictably get stuck in an undesirable operating point. Engineers often attempt to verify start-up effectiveness with transient simulations. This approach is heuristic and time consuming. Moreover, multiple operating points may still exist in circuits. All circuits we have studied with known need for start-up circuits have a positive feedback loop (PFL) as part of the self-stabilization process. As a result, we made a conjecture that, A circuit is vulnerable to the multiple operating points problem only if the circuit has one or more Positive Feedback Loops. A graphical method for identifying positive feedback loops in analog circuits is presented for the purpose of identifying the stable equilibrium points. Firstly, since our method is based on graphical concepts, some key terminologies from graph theory will be reviewed. Secondly, Graphical models for key analog components are developed and then hierarchically used to obtain a graphical representation of an analog circuit. Thirdly, the concept of determining positive feedback loops from the small-signal resistive Directed, Weighted, Multi-Graph (DWM Graph) of a circuit will be addressed. The three-step process will be used to determine the positive feedback loops. Lastly, a method for breaking positive feedback loop and how to apply the homotopy method to create a return map for the positive feedback loop is introduced. By breaking the positive feedback loop in the circuit and applying break-loop homotopy method, it can determine the uniqueness of operating points in self-biasing circuits. Sample-and-hold circuit is wildly used in mixed-signal circuits such as data converters, filters etc. Thermal noise is often a design limitation in mixed-signal designs. Many literatures and analog textbooks state that the thermal noise voltage sampled on a capacitor is where k is Boltzmann constant, T is temperature and C is capacitance [21][24]. From the expression of thermal noise voltage, we can find that thermal noise is highly related to the capacitor values and independent of resistors. The only way to reduce thermal noise voltage is to increase the capacitance. However, a large capacitor increases the settling time and reduce sampling rate. Meanwhile, layout area and power dissipation will be increased. There is a tradeoff between settling time and accuracy. No literatures introduce a method for reducing thermal noise without increasing capacitance. Reducing noise on a sampling capacitor below may give designers opportunities for improving system performance. A method for reducing thermal noise voltage on a sampling capacitor dramatically below is introduced. In high resolution SAR ADC design, many papers state that the minimum capacitance of capacitor DAC is determined by the thermal noise limitation. This thermal noise limitation is kT/C where k is Boltzmann constant, T is temperature and C is the total capacitance of capacitor DAC. Moreover, they assume this is the input-referred noise for the whole ADC. However, this calculation ignores the noise from charge-redistribution mode completely. Meanwhile, no literatures introduce any method about numerical calculation of thermal noise from charge-redistribution mode of capacitor DAC of SAR ADC. A numerical calculation of thermal noise from charge-redistribution mode of capacitor DAC of SAR ADC is introduced