High linearity analog and mixed-signal integrated circuit design

Linearity is one of the most important specifications in electrical circuits.;In Chapter 1, a ladder-based transconductance networks has been adopted first time to build a low distortion analog filters for low frequency applications. This new technique eliminated the limitation of the application with the traditional passive resistors for low frequency applications. Based on the understanding of this relationship, a strategy for designing high linear analog continuous-time filters has been developed. According to our strategy, a prototype analog integrated filter has been designed and fabricated with AMI05 0.5 um standard CMOS process. Experimental results proved this technique has the ability to provide excellent linearity with very limited active area.;In Chapter 2, the relationships between the transconductance networks and major circuit specifications have been explored. The analysis reveals the trade off between the silicon area saved by the transconductance networks and the some other important specifications such as linearity, noise level and the process variations of the overall circuit. Experimental results of discrete component circuit matched very well with our analytical outcomes to predict the change of linearity and noise performance associated with different transconductance networks.;The Chapter 3 contains the analysis and mathematical proves of the optimum passive area allocations for several most popular analog active filters. Because the total area is now manageable by the technique introduced in the Chapter 1, the further reduce of the total area will be very important and useful for efficient utilizing the silicon area, especially with the today\u27s fast growing area efficiency of the highly density digital circuits. This study presents the mathematical conclusion that the minimum passive area will be achieved with the equalized resistor and capacitor.;In the Chapter 4, a well recognized and highly honored current division circuit has been studied. Although it was claimed to be inherently linear and there are over 60 published works reported with high linearity based on this technique, our study discovered that this current division circuit can achieve, if proper circuit condition being managed, very limited linearity and all the experimental verified performance actually based on more general circuit principle. Besides its limitation, however, we invented a novel current division digital to analog converter (DAC) based on this technique. Benefiting from the simple circuit structure and moderate good linearity, a prototype 8-bit DAC was designed in TSMC018 0.2 um CMOS process and the post layout simulations exhibited the good linearity with very low power consumption and extreme small active area.;As the part of study of the output stage for the current division DAC discussed in the Chapter 4, a current mirror is expected to amplify the output current to drive the low resistive load. The strategy of achieving the optimum bandwidth of the cascode current mirror with fixed total current gain is discussed in the Chapter 5.;Improving the linearity of pipeline ADC has been the hottest and hardest topic in solid-state circuit community for decade. In the Chapter 6, a comprehensive study focus on the existing calibration algorithms for pipeline ADCs is presented. The benefits and limitations of different calibration algorithms have been discussed. Based on the understanding of those reported works, a new model-based calibration is delivered. The simulation results demonstrate that the model-based algorithms are vulnerable to the model accuracy and this weakness is very hard to be removed. From there, we predict the future developments of calibration algorithms that can break the linearity limitations for pipelined ADC. (Abstract shortened by UMI.

Programming of Floating-Gate Transistors for Nonvolatile Analog Memory Array

Since they were introduced, floating-gate (FG) transistors have been used as non-volatile digital memory. Recent research has shown that floating-gate transistors can be successfully used as analog memory, specifically as programmable voltage and current sources. However, their proliferation has been limited due to the complex programming procedure and the complex testing equipment. Analog applications such as field-programmable analog arrays (FPAAs) require hundreds to thousands of floating-gate transistors on a single chip which makes the programming process even more complicated and very challenging. Therefore, a simplified, compact, and low-power scheme to program FGs are necessary. This work presents an improved version of the typical methodology for FG programming. Additionally, a novel programming methodology that utilizes negative voltages is presented here. This method simplifies the programming process by eliminating the use of supplementary and complicated infrastructure circuits, which makes the FG transistor a good candidate for low-power wireless sensor nodes and portable systems

Validation and optimization of analog circuits using randomized search algorithms

Analog circuits represent a large percentage of the chips used in mobile computing, communication devices, electric vehicles, and portable medical equipment today. Rapid scaling and shrinking chip geometrics introduce new challenging problems in verification, validation, and optimization of analog circuits. These problems include test generation and compression, runtime monitoring and analyzing the worst-case behaviors. State of the art techniques in Monte Carlo are unable to address these problems effectively. Consequently, designing an efficient and scalable CAD algorithm to address such problems is highly desirable.  In this thesis, we introduce Duplex, a methodology for search and optimization. Duplex supports optimizing nonconvex nonlinear functions and functionals. We use duplex to solve problems in analog validation and machine learning. Duplex uses random tree data structures. Duplex is based on partitioning and separating the problem space into multiple smaller spaces such as input, state and the function space. Duplex simultaneously controls, biases and monitors the growth of the random trees in the partitioned spaces. We have used the duplex framework to solve practical problems in analog and mixed signal validation like directed input stimuli generation, compressing analog stress tests, worst-case eye diagram analysis, performance optimization, machine learning, and monitoring runtime behaviors of analog circuits. We used Duplex for validation and optimization of analog circuits. Duplex automatically generates input stimuli that expose bugs and improves coverage. Duplex automatically finds input corners that result in worst-case eye diagrams. Duplex simultaneously explores the parameter and performance spaces of analog circuits to optimize the circuit for best performance. We monitored the random trees and circuit execution against the specification properties described in formal languages. We formulated many challenging problems in the analog circuits, such as test compression and eye diagram analysis, as functional optimization problems. We use Duplex to solve these functional optimization problems.  We propose the Duplex algorithm as an optimization algorithm to posit the framework to other domains. Duplex can address nonlinear and functional optimization problems in continuous and discrete spaces such as design-space exploration and supervised and unsupervised machine learning. The advantages of the duplex framework are efficiency, scalability and versatility. We consistently show orders of magnitude speedup improvements over the state of the art while objectively improving the quality of results. For generating input stimuli, duplex is the first technique that simultaneously does directed input stimulus generation and increases test coverage. We show over two orders of magnitude speedup over Monte Carlo simulations. For runtime monitoring, we check a large scalable circuit against a very expressive set of formal properties that were not possible to monitor before. For generating worst-case eye diagram, we show at least $20\times$ speedup and better quality of results in comparison to the state of the art. Duplex is the first work to provide transient test compression for analog circuits. We compress stress tests up to 96\%. We optimize analog circuits using Duplex and we show speedup and improved results with respect to the state of the art. We use Duplex to train supervised and unsupervised models and show improved accuracy in all cases

Analog Spiking Neuromorphic Circuits and Systems for Brain- and Nanotechnology-Inspired Cognitive Computing

Human society is now facing grand challenges to satisfy the growing demand for computing power, at the same time, sustain energy consumption. By the end of CMOS technology scaling, innovations are required to tackle the challenges in a radically different way. Inspired by the emerging understanding of the computing occurring in a brain and nanotechnology-enabled biological plausible synaptic plasticity, neuromorphic computing architectures are being investigated. Such a neuromorphic chip that combines CMOS analog spiking neurons and nanoscale resistive random-access memory (RRAM) using as electronics synapses can provide massive neural network parallelism, high density and online learning capability, and hence, paves the path towards a promising solution to future energy-efficient real-time computing systems. However, existing silicon neuron approaches are designed to faithfully reproduce biological neuron dynamics, and hence they are incompatible with the RRAM synapses, or require extensive peripheral circuitry to modulate a synapse, and are thus deficient in learning capability. As a result, they eliminate most of the density advantages gained by the adoption of nanoscale devices, and fail to realize a functional computing system. This dissertation describes novel hardware architectures and neuron circuit designs that synergistically assemble the fundamental and significant elements for brain-inspired computing. Versatile CMOS spiking neurons that combine integrate-and-fire, passive dense RRAM synapses drive capability, dynamic biasing for adaptive power consumption, in situ spike-timing dependent plasticity (STDP) and competitive learning in compact integrated circuit modules are presented. Real-world pattern learning and recognition tasks using the proposed architecture were demonstrated with circuit-level simulations. A test chip was implemented and fabricated to verify the proposed CMOS neuron and hardware architecture, and the subsequent chip measurement results successfully proved the idea. The work described in this dissertation realizes a key building block for large-scale integration of spiking neural network hardware, and then, serves as a step-stone for the building of next-generation energy-efficient brain-inspired cognitive computing systems

A Low-Power, Reconfigurable, Pipelined ADC with Automatic Adaptation for Implantable Bioimpedance Applications

Biomedical monitoring systems that observe various physiological parameters or electrochemical reactions typically cannot expect signals with fixed amplitude or frequency as signal properties can vary greatly even among similar biosignals. Furthermore, advancements in biomedical research have resulted in more elaborate biosignal monitoring schemes which allow the continuous acquisition of important patient information. Conventional ADCs with a fixed resolution and sampling rate are not able to adapt to signals with a wide range of variation. As a result, reconfigurable analog-to-digital converters (ADC) have become increasingly more attractive for implantable biosensor systems. These converters are able to change their operable resolution, sampling rate, or both in order convert changing signals with increased power efficiency. Traditionally, biomedical sensing applications were limited to low frequencies. Therefore, much of the research on ADCs for biomedical applications focused on minimizing power consumption with smaller bias currents resulting in low sampling rates. However, recently bioimpedance monitoring has become more popular because of its healthcare possibilities. Bioimpedance monitoring involves injecting an AC current into a biosample and measuring the corresponding voltage drop. The frequency of the injected current greatly affects the amplitude and phase of the voltage drop as biological tissue is comprised of resistive and capacitive elements. For this reason, a full spectrum of measurements from 100 Hz to 10-100 MHz is required to gain a full understanding of the impedance. For this type of implantable biomedical application, the typical low power, low sampling rate analog-to-digital converter is insufficient. A different optimization of power and performance must be achieved. Since SAR ADC power consumption scales heavily with sampling rate, the converters that sample fast enough to be attractive for bioimpedance monitoring do not have a figure-of-merit that is comparable to the slower converters. Therefore, an auto-adapting, reconfigurable pipelined analog-to-digital converter is proposed. The converter can operate with either 8 or 10 bits of resolution and with a sampling rate of 0.1 or 20 MS/s. Additionally, the resolution and sampling rate are automatically determined by the converter itself based on the input signal. This way, power efficiency is increased for input signals of varying frequency and amplitude

Design of Neuromemristive Systems for Visual Information Processing

Neuromemristive systems (NMSs) are brain-inspired, adaptive computer architectures based on emerging resistive memory technology (memristors). NMSs adopt a mixed-signal design approach with closely-coupled memory and processing, resulting in high area and energy efficiencies. Previous work suggests that NMSs could even supplant conventional architectures in niche application domains such as visual information processing. However, given the infancy of the field, there are still several obstacles impeding the transition of these systems from theory to practice. This dissertation advances the state of NMS research by addressing open design problems spanning circuit, architecture, and system levels. Novel synapse, neuron, and plasticity circuits are designed to reduce NMSs’ area and power consumption by using current-mode design techniques and exploiting device variability. Circuits are designed in a 45 nm CMOS process with memristor models based on multilevel (W/Ag-chalcogenide/W) and bistable (Ag/GeS2/W) device data. Higher-level behavioral, power, area, and variability models are ported into MATLAB to accelerate the overall simulation time. The circuits designed in this work are integrated into neural network architectures for visual information processing tasks, including feature detection, clustering, and classification. Networks in the NMSs are trained with novel stochastic learning algorithms that achieve 3.5 reduction in circuit area, reduced design complexity, and exhibit similar convergence properties compared to the least-mean-squares algorithm. This work also examines the effects of device-level variations on NMS performance, which has received limited attention in previous work. The impact of device variations is reduced with a partial on-chip training methodology that enables NMSs to be configured with relatively sophisticated algorithms (e.g. resilient backpropagation), while maximizing their area-accuracy tradeoff

Embedded Systems for Photonic Cognitive Sensing

This research addresses challenges in two major applications, both related to photonic cognitive sensing. The first part, “Implantable Photonic Nano-Probe Detectors for Neural Imaging”, focuses on imaging system in the neural sciences field. The second part, “Advanced Control System for Optical Data Communications”, covers embedded low power control systems for optical communications. Implantable Photonic Nano-Probe Detectors for Neural Imaging This first part address the problem of simultaneous and real-time monitoring of dense brain neural activity, with the capability of cellular resolution and cell-type specificity included. For decades, electrophysiology has been the “gold standard” for the recording of neural activity. Despite recent advances, electrophysiology techniques can typically monitor fewer than 100 neurons simultaneously, due to the practical limits of electrode density. Additionally, the ability of direct monitoring specific cell types is not possible here. With the introduction of a growing panel of fluorescent optical reporters for brain function mapping, optical microscopy techniques have demonstrated the ability to track the activity of hundreds of neurons simultaneously in a much less invasive manner but with high spatial resolution, low-to-moderate temporal resolution and cell-type specificity. Unfortunately, only superficial layers of the brain can be imaged by free-space microscopy, due to the intrinsic light scattering and absorption limitation in brain tissue. To allow optical fluorescence imaging of deeper layers of the brain with proper a signal-to-noise ratio, a dense and scalable 3-D lattice of photo emitter and detector pixels (E-Pixels and D-Pixels, respectively) must be distributed on shanks for possible insertion into the brain. The 3-D lattice (combined fluorescent optical reporters) is expected to give an activity image of a very large neural population at an arbitrary depth in the brain. This work presents the design and implementation of the aforementioned 3-D photo- detectors (D-Pixels), associated with data processing and readout circuitries, for the future assembly of a probe-based system for functional imaging of neural activity. One of the main challenges of producing a probed-based version of a fluorescence microscope is the rejection of the light used to excite the fluorescent reporters. This is commonly done in the spectral domain with band-pass filters for free-space microscopy. However, these filters are not implementable with the proper optical density at the probe scale. The probe-based photo-detectors must be capable of rejecting the excitation light and capturing only the fluorescent response without the use of optical filters. Integrated Geiger-mode single-photon avalanche diodes (SPADs) are used as the sensing devices, which provide the ability to capture low fluorescence signals, fast response in the time domain, and direct digital readout. By engineering narrow E-Pixels angular-excitation fields and overlapping them with the narrow D-Pixels detection fields, fluorescent sources can be spatially localized. The detectors are embedded into four ultra-thin implantable shanks, associated with data processing units and readout circuits, all forming the photonic nano-probe detectors (also referred to as “D-Pixels Camera Chip (DCC)”). The shanks have dimensions of 110um×50um each, with 100 pixels along a shank (a total number of 400 pixels), distributed over 3mm length. The data generated by the photonic nano-probe detectors, is serially streamed out at a rate of 640Mbps, for offline analysis and image reconstruction. The photonic nano-probe detectors are fabricated in a conventional CMOS 0.13um technology. This part of the thesis first proposes and develops the architecture of the photonic nano-probe detectors. The challenges of designing high density, ultra-thin probes with the aforementioned form factor, fabricated in CMOS 0.13um technology is also discussed. Secondly, the design and implementation of testability and debugging options are mentioned, as playing an important role in achieving research goals. Last the design of lab experimental setups is presented and as well as the measurement results of the photonic nano-probe detectors. Experimental results indicate on achieving the crucial key features of the research work, the capability of rejecting the excitation light and capturing only the fluorescent decay response without the use of optical filters. Additionally, the results show that the photonic nano-probe detectors can precisely localize and map into a 2-D image, a light source within a pixel resolution.   Advanced Control System for Optical Data Communications The second part of the thesis focuses on the problem of initialization and temperature stabilization of silicon photonic (SiP) devices, with focus on dramatic power reduction of the power consumption. While microelectronics technology continues growing in scale, bandwidth, and integration of multiple systems on a single silicon die, the traditional electrical interconnects become the speed bottleneck in high-performance data communication systems. On the other hand, silicon photonics offers a promising platform for integration and manufacturing of photonics devices for high speed data transfer applications, such as access networks, supercomputers, chip-to-chip interconnects, and data centers. Additionally, the high index contrast of silicon platform and its compatibility with CMOS technologies, gives rise to integration of high speed, power efficient silicon photonic interconnects and most innovative CMOS technologies. Micro-ring resonators (MMRs), which are important building blocks is many silicon photonics applications, became attractive devices in many optical communication systems. This is due to their wavelength tuning ability, low power consumption and small footprint. However, temperature changes in their environment will shift their resonance from the desired point (due to high thermo-optical coupling in silicon), leading to performance degradation of the optical link. Compensating the degradation in performance can be directly translated to an excess in overall power consumption of the link, which will be critical in high-speed optical data communication systems. This work develops and demonstrates an ultra-low power control system, for initialization and temperature stabilization of MMRs. It utilizes an integrated heater, to thermally tune and lock the resonator to the desired wavelength. Traditional feedback loops rely on tapping a portion of the optical signal with the use of integrated photodiodes. They lock on the desired wavelength by sensing the maximum signal intensity, observed by the photodiode. The suggested control system in this work is based on an analog control system and utilizes the photo-conductance effect of doped-resistive heaters, to sense the optical power through the micro-ring. This part of the thesis first develops a VERILOG-A model for the photo-conductance effect of the doped-resistive heater. This enables the integration of the heater’s model with the proposed control circuits, into a circuit design simulator. Secondly, an architecture for the control system is proposed and developed, which includes fundamental electronic circuits with the aforementioned heater’s model. For the purpose of circuit level simulations, a design methodology is developed, which is based on semi-ideal models for the electronic building blocks. Then a circuit level simulator is used to simulate and evaluate the performance of the control system. Last, the proposed system is implemented with the use of commercial discrete electronic components, all connected on a custom designed printed circuit board (PCB). Simulations of the control system indicate an initialization time less than 160us, and maximum locking voltage error of 1.8%. The obtained dynamic energy consumption is ED=85 fJ/bit/oC for bit rate of 20Gbps. Though the control system is targeted for MRRs, it can be easily expanded to control other PIC devices

Duplex: Simultaneous Parameter-Performance Exploration for Optimizing Analog Circuits

We present Duplex random tree search, an algorithm to optimize performance metrics of analog and mixed signal circuits. Duplex determines the optimal design, the Pareto set, and the sensitivity of a circuit’s performance metrics to its parameters. We demonstrate that Duplex is 5x faster than the state-of-the-art and finds the global optimum for a design whose previously published result was a local optimum. We show our algorithm’s scalability by optimizing a system-level post-layout charged-pump PLL circuit.National Science Foundation / NSF CCF 14-23431Ope