A Novel Cyclic Time to Digital Converter Based on Triple-Slope Interpolation and Time Amplification

This paper investigates a novel cyclic time-to-digital converter (TDC) which employs triple-slope analog interpolation and time amplification techniques for digitizing the time interval between the rising edges of two input signals(Start and Stop). The proposed converter will be a 9-bit cyclic time-to-digital converter that does not use delay lines in its structure. Therefore, it has a low sensitivity to temperature, power supply and process (PVT) variations. The other advantages of the proposed converter are low circuit complexity, and high accuracy compared with the time-to-digital converters that have previously been proposed. Also, this converter improves the time resolution and the dynamic range. In the same resolution, linear range and dynamic range, the proposed cyclic TDC reduces the number of circuit elements compared with the converters that have a similar circuit structure. Thus, the converter reduces the chip area, the power consumption and the figure of merit (FoM). In this converter, the integral nonlinearity (INL) and differential nonlinearity (DNL) errors are reduced. In order to evaluate the idea, the proposed time-to-digital converter is designed in TSMC 45 nm CMOS technology and simulated. Comparison of the theoretical and simulation results confirms the benefits of the proposed TDC

Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin

A Fully Differential CMOS Potentiostat

A CMOS potentiostat for chemical sensing in a noisy environment is presented. The potentiostat measures bidirectional electrochemical redox currents proportional to the concentration of a chemical down to pico-ampere range. The fully differential architecture with differential recording electrodes suppresses the common mode interference. A 200μm×200μm prototype was fabricated in a standard 0.35μm standard CMOS technology and yields a 70dB dynamic range. The in-channel analog-to-digital converter (ADC) performs 16-bit current-tofrequency quantization. The integrated potentiostat functionality is validated in electrical and electrochemical experiments

Bio-inspired 0.35μm CMOS Time-to-Digital Converter with 29.3ps LSB

Time-to-digital converter (TDC) integrated circuit is introduced in this paper. It is based on chain of delay elements composing a regular scalable structure. The scheme is analogous to the sound direction sensitivity nerve system found in barn owl. The circuit occupies small silicon area, and its direct mapping from time to position-code makes conversion rates up to 500Msps possible. Specialty of the circuit is the structural and functional symmetry. Therefore the role of start and stop signals are interchangeable. In other words negative delay is acceptable: the circuit has no dead time problems. These are benefits of the biology model of the auditory scene representation in the bird's brain. The prototype chip is implemented in 0.35μm CMOS having less than 30ps single-shot resolution in the measurements.Hungarian National Research Foundation TS4085

A mixed-signal integrated circuit for FM-DCSK modulation

This paper presents a mixed-signal application-specific integrated circuit (ASIC) for a frequency-modulated differential chaos shift keying (FM-DCSK) communication system. The chip is conceived to serve as an experimental platform for the evaluation of the FM-DCSK modulation scheme, and includes several programming features toward this goal. The operation of the ASIC is herein illustrated for a data rate of 500 kb/s and a transmission bandwidth in the range of 17 MHz. Using signals acquired from the test platform, bit error rate (BER) estimations of the overall FM-DCSK communication link have been obtained assuming wireless transmission at the 2.4-GHz ISM band. Under all tested propagation conditions, including multipath effects, the system obtains a BER = 10-3 for Eb/No lower than 28 dB.Ministerio de Ciencia y Tecnología TIC2003-0235

Energy-efficiency improvements for optical access

This article discusses novel approaches to improve energy efficiency of different optical access technologies, including time division multiplexing passive optical network (TDM-PON), time and wavelength division multiplexing PON (TWDM-PON), point-to-point (PTP) access network, wavelength division multiplexing PON (WDM-PON), and orthogonal frequency division multiple access PON (OFDMA-PON). These approaches include cyclic sleep mode, energy-efficient bit interleaving protocol, power reduction at component level, or frequency band selection. Depending on the target optical access technology, one or a combination of different approaches can be applied

Comparator Design in Sensors for Environmental Monitoring

This paper presents circuit design considerations of comparator in analog-to-digital converters (ADC) applied for a portable, low-cost and high performance nano-sensor chip which can be applied to detect the airborne magnetite pollution nano particulate matter (PM) for environmental monitoring. High-resolution ADC plays a vital important role in high perfor-mance nano-sensor, while high-resolution comparator is a key component in ADC. In this work, some important design issues related to comparators in analog-to-digital converters (ADCs) are discussed, simulation results show that the resolution of the comparator proposed can achieve 5µV , and it is appropriate for high-resolution application

Design of the 12-bit Delta-Sigma Modulator using SC Technique for Vibration Sensor Output Processing

The work deals with the design of the 12-bit Delta-Sigma modulator using switched capacitors (SC) technique. The modulator serves to vibration sensor output processing. The first part describes the Delta-Sigma modulator parameters definition. Results of the proposed topology ideal model were presented as well. Next, the Delta-Sigma modulator circuitry on the transistor level was done. The ONSemiconductor I2T100 0.7 um CMOS technology was used for design. Then, the Delta-Sigma modulator nonidealities were simulated and implemented into the MATLAB ideal model of the modulator. The model of real Delta-Sigma modulator was derived. Consequently, modulator coefficients were optimized. Finally, the corner analysis of the Delta-Sigma modulator with the optimized coefficients was simulated. The value of SNDR = 82.2 dB (ENOB = 13.4 bits) was achieved