A self-powered single-chip wireless sensor platform

Internet of things” require a large array of low-cost sensor nodes, wireless connectivity, low power operation and system intelligence. On the other hand, wireless biomedical implants demand additional specifications including small form factor, a choice of wireless operating frequencies within the window for minimum tissue loss and bio-compatibility This thesis describes a low power and low-cost internet of things system suitable for implant applications that is implemented in its entirety on a single standard CMOS chip with an area smaller than 0.5 mm2. The chip includes integrated sensors, ultra-low-power transceivers, and additional interface and digital control electronics while it does not require a battery or complex packaging schemes. It is powered through electromagnetic (EM) radiation using its on-chip miniature antenna that also assists with transmit and receive functions. The chip can operate at a short distance (a few centimeters) from an EM source that also serves as its wireless link. Design methodology, system simulation and optimization and early measurement results are presented

Design of a 3 GHz fine resolution LC DCO

In this thesis, the design of a fine resolution LC digitally controlled oscillator (DCO) is introduced. Two NMOS varactor banks are used to achieve 12 bits medium and fine frequency tuning. Both delta-sigma modulator and capacitive divider circuit are implemented to achieve a finer resolution and a larger dynamic range. The LC-oscillator has a coarse tuning range from 3.05 GHz to 3.85 GHz and a fine tuning range of 50MHz. It features a phase noise level of -115dBc/Hz at 1MHz frequency offset and consumes 5.4mW. Efficient simulation methodology is explored. Finally, this DCO is simulated in an All-Digital Phase Locked Loop (ADPLL) with other ideal behavior blocks implemented using Verilog-A, and the performance of the DCO is evaluated.Electrical and Computer Engineerin

A low power signal front-end for passive UHF RFID transponders with a new clock recovery circuit.

Chan, Chi Fat.Thesis (M.Phil.)--Chinese University of Hong Kong, 2009.Includes bibliographical references.Abstracts in English and Chinese.Abstract --- p.2摘要 --- p.5Acknowledgement --- p.7Table of Contents --- p.9List of Figures --- p.11List of Tables --- p.14Chapter 1. --- Introduction --- p.15Chapter 1.2. --- Research Objectives --- p.16Chapter 1.3. --- Thesis Organization --- p.18Chapter 1.4. --- References --- p.19Chapter 2. --- Overview of Passive UHF RFID Transponders --- p.20Chapter 2.1. --- Types of RFID Transponders and Design Challenges of Passive RFID Transponder --- p.20Chapter 2.2. --- Selection of Carrier Frequency --- p.22Chapter 2.3. --- Description of Transponder Construction --- p.22Chapter 2.3.1. --- Power-Generating Circuits --- p.23Chapter 2.3.2. --- Base Band Processor --- p.28Chapter 2.3.3. --- Signal Front-End --- p.29Chapter 2.4. --- Summary --- p.30Chapter 2.5. --- References --- p.31Chapter 3. --- ASK Demodulator for EPC C-l G-2 Transponder --- p.32Chapter 3.1. --- ASK Demodulator Design Considerations --- p.32Chapter 3.1.1. --- Recovered Envelope Distortion --- p.32Chapter 3.1.2. --- Input Power Level Considerations --- p.34Chapter 3.1.3. --- Input RF power Intercepted by ASK Demodulator --- p.36Chapter 3.2. --- ASK Demodulator Design From [3-4] --- p.36Chapter 3.2.1. --- Envelope Waveform Recovery Design --- p.37Chapter 3.2.1.1. --- Voltage Multiplier Branch for Generating Venv --- p.39Chapter 3.2.1.2. --- Voltage Multiplier Branch for Generating Vref --- p.41Chapter 3.2.2. --- Design Considerations for Sensitivity of ASK Demodulator --- p.41Chapter 3.2.3. --- RF Input Power Sharing with Voltage Multiplier --- p.44Chapter 3.2.4. --- ASK Demodulator and Voltage Multiplier Integrated Estimations for Maximum RF Power Input --- p.47Chapter 3.2.5. --- Measurement result and Discussion --- p.49Chapter 3.3. --- Proposed Envelope Detector Circuit --- p.52Chapter 3.3.1. --- Sensitivity Estimation --- p.52Chapter 3.3.2. --- Maximum Tolerable Input Power Estimation --- p.53Chapter 3.3.3. --- Envelope Waveform Recovery of the Proposed Envelope Detector --- p.54Chapter 3.4. --- Summary --- p.57Chapter 3.5. --- References --- p.58Chapter 4. --- Clock Generator for EPC C-l G-2 Transponder --- p.59Chapter 4.1. --- Design Challenges Overview of Clock Generator --- p.59Chapter 4.2. --- Brief Review of PIE Symbols in EPC C1G2 Standard --- p.62Chapter 4.3. --- Proposed Clock Recovery Circuit Based on PIE Symbols for Clock Frequency Calibration --- p.64Chapter 4.3.1. --- Illustration on PIE Symbols for Clock Frequency Calibration --- p.64Chapter 4.3.2. --- Symbol time-length counter --- p.72Chapter 4.3.3. --- The M2.56MHZ Reference Generator and Sampling Frequency Requirement --- p.75Chapter 4.3.4. --- Symbol Length Reconfiguration for Different Tari and FLL Stability --- p.80Chapter 4.3.5. --- Frequency Detector and Loop Filter --- p.83Chapter 4.3.6. --- Proposed DCO Design --- p.84Chapter 4.3.7. --- Measurement Results and Discussions --- p.88Chapter 4.3.7.1. --- Frequency Calibration Measurement Results --- p.89Chapter 4.3.7.2. --- Number x and Tari Variation --- p.92Chapter 4.3.7.3. --- Temperature and Supply Variation --- p.93Chapter 4.3.7.4. --- Transient Supply Variation --- p.94Chapter 4.3.8. --- Works Comparison --- p.95Chapter 4.4. --- Clock Generator with Embedded PIE Decoder --- p.96Chapter 4.4.1. --- Clock Generator for Transponder Review --- p.96Chapter 4.4.2. --- PIE Decoder Review --- p.97Chapter 4.4.3. --- Proposed Clock Generator with Embedded PIE Decoder --- p.97Chapter 4.4.4. --- Measurement Results and Discussions --- p.100Chapter 4.5. --- Summary --- p.103Chapter 4.6. --- References --- p.105Chapter 5. --- ASK Modulator --- p.107Chapter 5.1. --- Introduction to ASK Modulator in RFD Transponder --- p.107Chapter 5.2. --- ASK Modulator Design --- p.109Chapter 5.3. --- ASK Modulator Measurement --- p.110Chapter 5.4. --- Summary --- p.113Chapter 5.5. --- References --- p.113Chapter 6. --- Conclusions --- p.114Chapter 6.1. --- Contribution --- p.114Chapter 6.2. --- Future Development --- p.11

A Methodology for Implementing RF BiSTs in Production Testing to Replace RF Conventional Tests

Production testing of Radio Frequency (RF) devices is challenging due to the complex nature of the tests that have to be performed to verify functionality. In this dissertation a methodology to replace the complex and expensive RF functional tests with defect-oriented Built-in Self Tests (BiSTs) is detailed. If a design has sufficient margin to RF specifications then RF tests can be replaced with structural tests using a new data analysis technique called quadrant analysis, which is presented. Data from the analysis of over one million production units of said System on Chip (SoC) is presented along with the results of the analysis. The BiST techniques that have been used are discussed and a Texas Instruments 65 nm RF SoC with a Bluetooth and a FM core was used as a case study. The defect models that were used to develop the BiSTs are discussed as well. The scenario in which a design does not have sufficient margin to specification is also discussed. The data analysis method required in such a case is a regression analysis and the data from such an analysis is shown. The results prove that it is possible to replace expensive RF conventional tests with structural tests and that modern RFCMOS process technology and advances in design like the Digital Radio Processor (DRPTM) technology enable this. The Defective Parts Per Million (DPPM) impact of making this replacement is 27 units and is acceptable for RFCMOS high volume products. Finally, data showing test cost reduction of about 38% that resulted from the elimination of RF conventional tests is presented

RF CMOS Oscillators for Modern Wireless Applications

While mobile phones enjoy the largest production volume ever of any consumer electronics products, the demands they place on radio-frequency (RF) transceivers are particularly aggressive, especially on integration with digital processors, low area, low power consumption, while being robust against process-voltage-temperature variations. Since mobile terminals inherently operate on batteries, their power budget is severely constrained. To keep up with the ever increasing data-rate, an ever-decreasing power per bit is required to maintain the battery lifetime. The RF oscillator is the second most power-hungry block of a wireless radio (after power amplifiers). Consequently, any power reduction in an RF oscillator will greatly benefit the overall power efficiency of the cellular transceiver. Moreover, the RF oscillators' purity limits the transceiver performance. The oscillator's phase noise results in power leakage into adjacent channels in a transmit mode and reciprocal mixing in a receive mode. On the other hand, the multi-standard and multi-band transceivers that are now trending demand wide tuning range oscillators. However, broadening the oscillator’s tuning range is usually at the expense of die area (cost) or phase noise. The main goal of this book is to bring forth the exciting and innovative RF oscillator structures that demonstrate better phase noise performance, lower cost, and higher power efficiency than currently achievable. Technical topics discussed in RF CMOS Oscillators for Modern Wireless Applications include: Design and analysis of low phase-noise class-F oscillators Analyze a technique to reduce 1/f noise up-conversion in the oscillators Design and analysis of low power/low voltage oscillators Wide tuning range oscillators Reliability study of RF oscillators in nanoscale CMO

High-Resolution mm-wave Digitally Controlled Oscillator in CMOS

All-digital PLLs promise flexible and precise frequency modulation continous-wave(FMCW) radar signal signal for 77GHz radar applications. Such PLLs require digitally-controlled oscillators(DCO) with wide frequency tuning range and high resolution to address a range of applications and low phase noise requirements. In this thesis, novel resonator structures with ne capacitance/inductance switching are embedded in a wide FTR common-source Colpitts DCO to achieve sub-MHz DCO frequency resolution at 77GHz. The proposed structures also reduce dependence on switch-position for frequency step size, simplifying calibration. Besides, three di erent oscillator topologies are compared, and an optimized oscillator structure is used to improve DCO gure of merit. The DCO implemented in 65nm CMOS occupies 0.1mm² and consumes 15.6mW to achieve phase noise of -115dBc/Hz at 10MHz o set at 80GHz and state-of-the-art mm-wave DCO FoM-T of -182dBc/Hz

Ultra-Low Power Transmitter and Power Management for Internet-of-Things Devices

Two of the most critical components in an Internet-of-Things (IoT) sensing and transmitting node are the power management unit (PMU) and the wireless transmitter (Tx). The desire for longer intervals between battery replacements or a completely self-contained, battery-less operation via energy harvesting transducers and circuits in IoT nodes demands highly efficient integrated circuits. This dissertation addresses the challenge of designing and implementing power management and Tx circuits with ultra-low power consumption to enable such efficient operation. The first part of the dissertation focuses on the study and design of power management circuits for IoT nodes. This opening portion elaborates on two different areas of the power management field: Firstly, a low-complexity, SPICE-based model for general low dropout (LDO) regulators is demonstrated. The model aims to reduce the stress and computation times in the final stages of simulation and verification of Systems-on-Chip (SoC), including IoT nodes, that employ large numbers of LDOs. Secondly, the implementation of an efficient PMU for an energy harvesting system based on a thermoelectric generator transducer is discussed. The PMU includes a first-in-its-class LDO with programmable supply noise rejection for localized improvement in the suppression. The second part of the dissertation addresses the challenge of designing an ultra- low power wireless FSK Tx in the 900 MHz ISM band. To reduce the power consumption and boost the Tx energy efficiency, a novel delay cell exploiting current reuse is used in a ring-oscillator employed as the local oscillator generator scheme. In combination with an edge-combiner PA, the Tx showed a measured energy efficiency of 0.2 nJ/bit and a normalized energy efficiency of 3.1 nJ/(bit∙mW) when operating at output power levels up to -10 dBm and data rates of 3 Mbps. To close this dissertation, the implementation of a supply-noise tolerant BiCMOS ring-oscillator is discussed. The combination of a passive, high-pass feedforward path from the supply to critical nodes in the selected delay cell and a low cost LDO allow the oscillator to exhibit power supply noise rejection levels better than –33 dB in experimental results

RF CMOS Oscillators for Modern Wireless Applications

While mobile phones enjoy the largest production volume ever of any consumer electronics products, the demands they place on radio-frequency (RF) transceivers are particularly aggressive, especially on integration with digital processors, low area, low power consumption, while being robust against process-voltage-temperature variations. Since mobile terminals inherently operate on batteries, their power budget is severely constrained. To keep up with the ever increasing data-rate, an ever-decreasing power per bit is required to maintain the battery lifetime. The RF oscillator is the second most power-hungry block of a wireless radio (after power amplifiers). Consequently, any power reduction in an RF oscillator will greatly benefit the overall power efficiency of the cellular transceiver. Moreover, the RF oscillators' purity limits the transceiver performance. The oscillator's phase noise results in power leakage into adjacent channels in a transmit mode and reciprocal mixing in a receive mode. On the other hand, the multi-standard and multi-band transceivers that are now trending demand wide tuning range oscillators. However, broadening the oscillator’s tuning range is usually at the expense of die area (cost) or phase noise. The main goal of this book is to bring forth the exciting and innovative RF oscillator structures that demonstrate better phase noise performance, lower cost, and higher power efficiency than currently achievable. Technical topics discussed in RF CMOS Oscillators for Modern Wireless Applications include: Design and analysis of low phase-noise class-F oscillators Analyze a technique to reduce 1/f noise up-conversion in the oscillators Design and analysis of low power/low voltage oscillators Wide tuning range oscillators Reliability study of RF oscillators in nanoscale CMO

Design of ASIC Based Electrical Impedance Tomography Microendoscopic System for Prostate Cancer Surgical Marginal Assessment

Prostate cancer is the second most common cancer in the United States. It is typically treated by surgically excising the cancerous section of the prostate. Because there is not always a visible distinction between the healthy and cancerous sections, surgery often leaves some cancerous tissue behind. This is referred to as a positive surgical margin and it requires adjuvant treatment with adverse side effects. Electrical impedance tomography (EIT) is a low-cost low-form-factor method that can be used to assess surgical marginal intraoperatively to ensure that no cancerous tissue is left behind. EIT-based surgical margin assessment works on the principle that the electrical properties of cancerous tissue are different from those of healthy tissue. These differences are small at lower frequencies but become more pronounced at frequencies of 1 MHz and higher. Unfortunately, previous EIT solutions for surgical marginal assessment have been limited to operating frequencies of less than 1 MHz. This thesis presents a custom application-specific integrated circuit (ASIC) analog front end for performing EIT with a signal-to-noise ratio of 75 dB up to an operating frequency of 10 MHz. The custom ASIC was integrated into a 16-electrode EIT system for surgical marginal assessment. The entire system was tested on a saline phantom with a 2 mm bead that represented a cancerous lesion. The EIT system produced single-frequency and multi-frequency images showing the presence of the inclusion

Relaxation Digital-to-Analog Converter with Radix-based Digital Correction

A Relaxation Digital-to-Analog Converter (ReDACs) with a novel, all-digital, radix-based digital correction technique for clock-indifferent linear operation is presented in this paper. The ReDAC architecture proposed in this paper does not require dedicated circuit for frequency tuning, and achieves linearity by digitally pre-processing the DAC input code by a Radix-based Digital Correction (RBDC) algorithm. The effectiveness of the proposed RBDC approach is demonstrated by transistor level simulations on a 10-bit, 1.7MS/s ReDAC in 180nm CMOS. Thanks to the proposed RBDC, under a 16% deviation from the ideal clock period, the maximum INL of the ReDAC is improved from 79.4 to 1.01LSB, its maximum DNL is improved from 158.3 to 0.45LSB and its SNDR is increased from 22.2 (3.4 ENOB) to 58.5dB (9.4 ENOB), at the cost of an increased power consumption from 1.85μW to 9.15μW