Amplifiers in Biomedical Engineering: A Review from Application Perspectives

Continuous monitoring and treatment of various diseases with biomedical technologies and wearable electronics has become significantly important. The healthcare area is an important, evolving field that, among other things, requires electronic and micro-electromechanical technologies. Designed circuits and smart devices can lead to reduced hospitalization time and hospitals equipped with high-quality equipment. Some of these devices can also be implanted inside the body. Recently, various implanted electronic devices for monitoring and diagnosing diseases have been presented. These instruments require communication links through wireless technologies. In the transmitters of these devices, power amplifiers are the most important components and their performance plays important roles. This paper is devoted to collecting and providing a comprehensive review on the various designed implanted amplifiers for advanced biomedical applications. The reported amplifiers vary with respect to the class/type of amplifier, implemented CMOS technology, frequency band, output power, and the overall efficiency of the designs. The purpose of the authors is to provide a general view of the available solutions, and any researcher can obtain suitable circuit designs that can be selected for their problem by reading this survey

Low-power Design of a Neuromorphic IC and MICS Transceiver

abstract: The first part describes Metal Semiconductor Field Effect Transistor (MESFET) based fundamental analog building blocks designed and fabricated in a single poly, 3-layer metal digital CMOS technology utilizing fully depletion mode MESFET devices. DC characteristics were measured by varying the power supply from 2.5V to 5.5V. The measured DC transfer curves of amplifiers show good agreement with the simulated ones with extracted models from the same process. The accuracy of the current mirror showing inverse operation is within ±15% for the current from 0 to 1.5mA with the power supply from 2.5 to 5.5V. The second part presents a low-power image recognition system with a novel MESFET device fabricated on a CMOS substrate. An analog image recognition system with power consumption of 2.4mW/cell and a response time of 6µs is designed, fabricated and characterized. The experimental results verified the accuracy of the extracted SPICE model of SOS MESFETs. The response times of 4µs and 6µs for one by four and one by eight arrays, respectively, are achieved with the line recognition. Each core cell for both arrays consumes only 2.4mW. The last part presents a CMOS low-power transceiver in MICS band is presented. The LNA core has an integrated mixer in a folded configuration. The baseband strip consists of a pseudo differential MOS-C band-pass filter achieving demodulation of 150kHz-offset BFSK signals. The SRO is used in a wakeup RX for the wake-up signal reception. The all digital frequency-locked loop drives a class AB power amplifier in a transmitter. The sensitivity of -85dBm in the wakeup RX is achieved with the power consumption of 320µW and 400µW at the data rates of 100kb/s and 200kb/s from 1.8V, respectively. The sensitivities of -70dBm and -98dBm in the data-link RX are achieved with NF of 40dB and 11dB at the data rate of 100kb/s while consuming only 600µW and 1.5mW at 1.2V and 1.8V, respectively.Dissertation/ThesisPh.D. Electrical Engineering 201

Advanced sensors technology survey

This project assesses the state-of-the-art in advanced or 'smart' sensors technology for NASA Life Sciences research applications with an emphasis on those sensors with potential applications on the space station freedom (SSF). The objectives are: (1) to conduct literature reviews on relevant advanced sensor technology; (2) to interview various scientists and engineers in industry, academia, and government who are knowledgeable on this topic; (3) to provide viewpoints and opinions regarding the potential applications of this technology on the SSF; and (4) to provide summary charts of relevant technologies and centers where these technologies are being developed

A 0.18-μm BICMOS 20-57 GHz Ultra-Wideband Low-Noise Amplifier Utilizing Frequency-Controlled Positive-Negative Feedback Technique

Silicon based complementary metallic oxide semiconductor (CMOS) and Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) radio frequency integrated circuits (RFICs), including microwave and millimeter-wave (MMW), are attractive for wireless communication and sensing systems due to their small chip size and facilitation in system-on-chip integration. One of the most important RFICs is the low-noise amplifier (LNA). The design of CMOS/BiCMOS wideband LNAs at MMW frequencies, especially those working across several decades of frequency, is challenging due to various issues. For instance, the device parasitic and inter-coupling between nearby elements in highly condensed chip areas limits the operating bandwidth and performance, and the conductive silicon substrates lead to the inevitable low quality factor of passive elements. In this work, a MMW BiCMOS ultra-wideband LNA across 20 to 57 GHz is presented along with the analysis, design and measurement results. To overcome the upper-band gain degradation and improve the in-band flatness, a novel frequency controlled positive-negative (P-N) feedback topology is adopted to modify the gain response by boosting the gain at the upper-band while suppressing that at the lower-band. To reduce overall power consumption, the first and second stages of the amplifier are stacked between supply voltage and DC ground to utilize the same DC current. At the output of amplifier, a shunt-peaking load stage is utilized to achieve wideband output matching. The designed ultra-wideband MMW LNA is fabricated in JAZZ 0.18-μm BiCMOS technology. It shows a measured power gain of 10.5 ± 0.5 dB, a noise figure between 5.1-7.0 dB, input and output return losses better than -10 and -15 dB, respectively, an input 1 dB compression point higher than -19 dBm, and an input third-order intercept point greater than -8 dBm. It dissipates 16.6 mW from 1.8 V DC supply and has a chip area of 700×400 μm^2

A 0.18-μm BICMOS 20-57 GHz Ultra-Wideband Low-Noise Amplifier Utilizing Frequency-Controlled Positive-Negative Feedback Technique

Silicon based complementary metallic oxide semiconductor (CMOS) and Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) radio frequency integrated circuits (RFICs), including microwave and millimeter-wave (MMW), are attractive for wireless communication and sensing systems due to their small chip size and facilitation in system-on-chip integration. One of the most important RFICs is the low-noise amplifier (LNA). The design of CMOS/BiCMOS wideband LNAs at MMW frequencies, especially those working across several decades of frequency, is challenging due to various issues. For instance, the device parasitic and inter-coupling between nearby elements in highly condensed chip areas limits the operating bandwidth and performance, and the conductive silicon substrates lead to the inevitable low quality factor of passive elements. In this work, a MMW BiCMOS ultra-wideband LNA across 20 to 57 GHz is presented along with the analysis, design and measurement results. To overcome the upper-band gain degradation and improve the in-band flatness, a novel frequency controlled positive-negative (P-N) feedback topology is adopted to modify the gain response by boosting the gain at the upper-band while suppressing that at the lower-band. To reduce overall power consumption, the first and second stages of the amplifier are stacked between supply voltage and DC ground to utilize the same DC current. At the output of amplifier, a shunt-peaking load stage is utilized to achieve wideband output matching. The designed ultra-wideband MMW LNA is fabricated in JAZZ 0.18-μm BiCMOS technology. It shows a measured power gain of 10.5 ± 0.5 dB, a noise figure between 5.1-7.0 dB, input and output return losses better than -10 and -15 dB, respectively, an input 1 dB compression point higher than -19 dBm, and an input third-order intercept point greater than -8 dBm. It dissipates 16.6 mW from 1.8 V DC supply and has a chip area of 700×400 μm^2

Signal amplification, detection and transmission in a wireless 100-electrode neural recording system

Journal ArticleWe are developing a fully-implantable neural recording system with wireless power and data transfer. As part of this system, we have developed a low-power integrated circuit that performs power rectification and and regulation, reception of configuration data, neural signal amplification and filtering, spike detection, neural signal digitization and RF transmission. The chip includes 88 amplifiers having a gain of 60 dB from 1 to 5 kHz. An integrated ADC operates at 15 kSamples/sec with 9-bit resolution. A 433-MHz RF transmitter uses FSK The modulation to transmit one digitized neural signal and spike detection data from all channels. Total power consumption is 13.5 mW

Multi-channel ultra-low-power receiver architecture for body area networks

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.Cataloged from PDF version of thesis.Includes bibliographical references (p. 85-91).In recently published integrated medical monitoring systems, a common thread is the high power consumption of the radio compared to the other system components. This observation is indicative of a natural place to attempt a reduction in system power. Narrowband receivers in-particular can enjoy significant power reduction by employing high-Q bulk acoustic resonators as channel select filters directly at RF, allowing down-stream analog processing to be simplified, resulting in better energy efficiency. But for communications in the ISM bands, it is important to employ multiple frequency channels to permit frequency-division-multiplexing and provide frequency diversity in the face of narrowband interferers. The high-Q nature of the resonators means that frequency tuning to other channels in the same band is nearly impossible; hence, a new architecture is required to address this challenge. A multi-channel ultra-low power OOK receiver for Body Area Networks (BANs) has been designed and tested. The receiver multiplexes three Film Bulk Acoustic Resonators (FBARs) to provide three channels of frequency discrimination, while at the same time offering competitive sensitivity and superior energy efficiency in this class of BAN receivers. The high-Q parallel resonance of each resonator determines the passband. The resonator's Q is on the order of 1000 and its center frequency is approximately 2.5 GHz, resulting in a -3 dB bandwidth of roughly 2.5 MHz with a very steep rolloff. Channels are selected by enabling the corresponding LNA and mixer pathway with switches, but a key benefit of this architecture is that the switches are not in series with the resonator and do not de-Q the resonance. The measured 1E-3 sensitivity is -64 dBm at 1 Mbps for an energy efficiency of 180 pJ/bit. The resonators are packaged beside the CMOS using wirebonds for the prototype.by Phillip Michel Nadeau.S.M