Removing non-stationary noise in spectrum sensing using matrix factorization

Spectrum sensing is key to many applications like dynamicspectrum access (DSA) systems or telecom regulators who need to measure utilization of frequency bands. The International Telecommunication Union (ITU) recommends a 10 dB threshold above the noise to decide whether a channel is occupied or not. However, radio frequency (RF) receiver front-ends are non-ideal. This means that the obtained data is distorted with noise and imperfections from the analog front-end. As part of the front-end the automatic gain control (AGC) circuitry mainly affects the sensing performance as strong adjacent signals lift the noise level. To enhance the performance of spectrum sensing significantly we focus in this article on techniques to remove the noise caused by the AGC from the sensing data. In order to do this we have applied matrix factorization techniques, i.e., SVD (singular value decomposition) and NMF (non-negative matrix factorization), which enables signal space analysis. In addition, we use live measurement results to verify the performance and to remove the effects of the AGC from the sensing data using above mentioned techniques, i.e., applied on block-wise available spectrum data. In this article it is shown that the occupancy in the industrial, scientific and medical (ISM) band, obtained by using energy detection (ITU recommended threshold), can be an overestimation of spectrum usage by 60%

Low Power Analog Processing for Ultra-High-Speed Receivers with RF Correlation

Ultra-high-speed data communication receivers (Rxs) conventionally require analog digital converters (ADC)s with high sampling rates which have design challenges in terms of adequate resolution and power. This leads to ultra-high-speed Rxs utilising expensive and bulky high-speed oscilloscopes which are extremely inefficient for demodulation, in terms of power and size. Designing energy-efficient mixed-signal and baseband units for ultra-high-speed Rxs requires a paradigm approach detailed in this paper that circumvents the use of power-hungry ADCs by employing low-power analog processing. The low-power analog Rx employs direct-demodulation with RF correlation using low-power comparators. The Rx is able to support multiple modulations with highest modulation of 16-QAM reported so far for direct-demodulation with RF correlation. Simulations using Matlab, Simulink R2020a® indicate sufficient symbol-error rate (SER) performance at a symbol rate of 8 GS/s for the 71 GHz Urban Micro Cell and 140 GHz indoor channels. Power analysis undertaken with current analog, hybrid and digital beamforming approaches requiring ADCs indicates considerable power savings. This novel approach can be adopted for ultra-high-speed Rxs envisaged for beyond fifth generation (B5G)/sixth generation (6G)/ terahertz (THz) communication without the power-hungry ADCs, leading to low-power integrated design solutions

Multi-gigabit CMOS analog-to-digital converter and mixed-signal demodulator for low-power millimeter-wave communication systems

The objective of the research is to develop high-speed ADCs and mixed-signal demodulator for multi-gigabit communication systems using millimeter-wave frequency bands in standard CMOS technology. With rapid advancements in semiconductor technologies, mobile communication devices have become more versatile, portable, and inexpensive over the last few decades. However, plagued by the short lifetime of batteries, low power consumption has become an extremely important specification in developing mobile communication devices. The ever-expanding demand of consumers to access and share information ubiquitously at faster speeds requires higher throughputs, increased signal-processing functionalities at lower power and lower costs. In today’s technology, high-speed signal processing and data converters are incorporated in almost all modern multi-gigabit communication systems. They are key enabling technologies for scalable digital design and implementation of baseband signal processors. Ultimately, the merits of a high performance mixed-signal receiver, such as data rate, sensitivity, signal dynamic range, bit-error rate, and power consumption, are directly related to the quality of the embedded ADCs. Therefore, this dissertation focuses on the analysis and design of high-speed ADCs and a novel broadband mixed-signal demodulator with a fully-integrated DSP composed of low-cost CMOS circuitry. The proposed system features a novel dual-mode solution to demodulate multi-gigabit BPSK and ASK signals. This approach reduces the resolution requirement of high-speed ADCs, while dramatically reducing its power consumption for multi-gigabit wireless communication systems.PhDGee-Kung Chang - Committee Chair; Chang-Ho Lee - Committee Member; Geoffrey Ye Li - Committee Member; Paul A. Kohl - Committee Member; Shyh-Chiang Shen - Committee Membe

CMOS ASIC Design of Multi-frequency Multi-constellation GNSS Front-ends

With the emergence of the new global navigation satellite systems (GNSSs) such as Galileo, COMPASS and GLONASS, the US Global Positioning System (GPS) has new competitors. This multiplicity of constellations will offer new services and a much better satellite coverage. Public regulated service (PRS) is one of these new services that Galileo, the first global positioning service under civilian control, will offers. The PRS is a proprietary encrypted navigation designed to be more reliable and robust against jamming and provides premium quality in terms of position and timing and continuity of service, but it requires the use of FEs with extended capabilities. The project that this thesis starts from, aims to develop a dual frequency (E1 and E6) PRS receiver with a focus on a solution for professional applications that combines affordability and robustness. To limit the production cost, the choice of a monolithic design in a multi-purpose 0.18 µm complementary metal-oxide-semiconductor (CMOS) technology have been selected, and to reduce the susceptibility to interference, the targeted receiver is composed of two independent FEs. The first ASIC described here is such FEs bundle. Each FE is composed of a radio frequency (RF) chain that includes a low-noise amplifier (LNA), a quadrature mixer, a frequency synthesizer (FS), two intermediate frequency (IF) filters, two variable-gain amplifiers (VGAs) and two 6-bit flash analog-to-digital converters (ADCs). Each have an IF bandwidth of 50 MHz to accommodate the wide-band PRS signals. The FE achieves a 30 dB of dynamic gain control at each channel. The complete receivers occupies a die area of 11.5 mm2 while consuming 115 mW from a supply of a 1.8 V. The second ASIC that targets civilian applications, is a reconfigurable single-channel FE that permits to exploit the interoperability among GNSSs. The FE can operate in two modes: a ¿narrow-band mode¿, dedicated to Beidou-B1 with an IF bandwidth of 8 MHz, and a ¿wide-band mode¿ with an IF bandwidth of 23 MHz, which can accommodate simultaneous reception of Beidou-B1/GPS-L1/Galileo-E1. These two modes consumes respectively 22.85 mA and 28.45 mA from a 1.8 V supply. Developed with the best linearity in mind, the FE shows very good linearity with an input-referred 1 dB compression point (IP1dB) of better than -27.6 dBm. The FE gain is stepwise flexible from 39 dB and to a maximum of 58 dB. The complete FE occupies a die area of only 2.6 mm2 in a 0.18 µm CMOS. To also accommodate the wide-band PRS signals in the IF section of the FE, a highly selective wide-tuning-range 4th-order Gm-C elliptic low-pass filter is used. It features an innovative continuous tuning circuit that adjusts the bias current of the Gm cell¿s input stage to control the cutoff frequency. With this circuit, the power consumption is proportional to the cutoff frequency thus the power efficiency is achieved while keeping the linearity near constant. Thanks to a Gm switching technique, which permit to keep the signal path switchless, the filter shows an extended tuning of the cutoff frequency that covers continuously a range from 7.4 MHz to 27.4 MHz. Moreover the abrupt roll-off of up to 66 dB/octave, can mitigate out-of-band interference. The filter consumes 2.1 mA and 7.5 mA at its lowest and highest cutoff frequencies respectively, and its active area occupies, 0.23 mm2. It achieves a high input-referred third-order intercept point (IIP3) of up to -1.3 dBVRMS

A Framework to Analyze Energy Efficiency of Multi-Band Spectrum Sensing Algorithms

Cognitive radio (CR) is a device which can detect wireless communication channels that are not in use and adapt its parameters intelligently. Networks with CRs use the available frequency bands much more efficiently and hence have higher data rates compare to traditional radios. Spectrum sensing is the class of techniques used by CRs to understand its wireless environment. Recent research on evaluating multi-band spectrum sensing algorithms is limited to only algorithm complexity and optimization; therefore, the primary goal of the study is to devise a novel framework that analyzes a multi-band spectrum sensing algorithm in terms of energy consumption and algorithm efficiency. The proposed structure leads to a comparison and evaluation of a large class of multi-band spectrum sensing algorithms. Multi-band spectrum sensing search methods such as linear, random and binary are evaluated for energy loss and detection performance using the proposed framework