A 0.6V 2.9µW mixed-signal front-end for ECG monitoring

This paper presents a mixed-signal ECG front-end that uses aggressive voltage scaling to maximize power-efficiency and facilitate integration with low-voltage DSPs. 50/60Hz interference is canceled using mixed-signal feedback, enabling ultra-low-voltage operation by reducing dynamic range requirements. Analog circuits are optimized for ultra-low-voltage, and a SAR ADC with a dual-DAC architecture eliminates the need for a power-hungry ADC buffer. Oversampling and ΔΣ-modulation leveraging near-V[subscript T] digital processing are used to achieve ultra-low-power operation without sacrificing noise performance and dynamic range. The fully-integrated front-end is implemented in a 0.18μm CMOS process and consumes 2.9μW from 0.6V.Texas Instruments IncorporatedNatural Sciences and Engineering Research Council of Canada (Fellowship

Energy Efficiency in Communications and Networks

The topic of "Energy Efficiency in Communications and Networks" attracts growing attention due to economical and environmental reasons. The amount of power consumed by information and communication technologies (ICT) is rapidly increasing, as well as the energy bill of service providers. According to a number of studies, ICT alone is responsible for a percentage which varies from 2% to 10% of the world power consumption. Thus, driving rising cost and sustainability concerns about the energy footprint of the IT infrastructure. Energy-efficiency is an aspect that until recently was only considered for battery driven devices. Today we see energy-efficiency becoming a pervasive issue that will need to be considered in all technology areas from device technology to systems management. This book is seeking to provide a compilation of novel research contributions on hardware design, architectures, protocols and algorithms that will improve the energy efficiency of communication devices and networks and lead to a more energy proportional technology infrastructure

A 32-Channel Time-Multiplexed Artifact-Aware Neural Recording System

This paper presents a low-power, low-noise microsystem for the recording of neural local field potentials or intracranial electroencephalographic signals. It features 32 time-multiplexed channels at the electrode interface and offers the possibility to spatially delta encode data to take advantage of the large correlation of signals captured from nearby channels. The circuit also implements a mixed-signal voltage-triggered auto-ranging algorithm which allows to attenuate large interferers in digital domain while preserving neural information. This effectively increases the system dynamic range and avoids the onset of saturation. A prototype, fabricated in a standard 180 nm CMOS process, has been experimentally verified in-vitro with cellular cultures of primary cortical neurons from mice. The system shows an integrated input-referred noise in the 0.5–200 Hz band of 1.4 µVrms for a spot noise of about 85 nV / √Hz. The system draws 1.5 µW per channel from 1.2 V supply and obtains 71 dB + 26 dB dynamic range when the artifact-aware auto-ranging mechanism is enabled, without penalising other critical specifications such as crosstalk between channels or common-mode and power supply rejection ratios

Ultra-low power mixed-signal frontend for wearable EEGs

Electronics circuits are ubiquitous in daily life, aided by advancements in the chip design industry, leading to miniaturised solutions for typical day to day problems. One of the critical healthcare areas helped by this advancement in technology is electroencephalography (EEG). EEG is a non-invasive method of tracking a person's brain waves, and a crucial tool in several healthcare contexts, including epilepsy and sleep disorders. Current ambulatory EEG systems still suffer from limitations that affect their usability. Furthermore, many patients admitted to emergency departments (ED) for a neurological disorder like altered mental status or seizures, would remain undiagnosed hours to days after admission, which leads to an elevated rate of death compared to other conditions. Conducting a thorough EEG monitoring in early-stage could prevent further damage to the brain and avoid high mortality. But lack of portability and ease of access results in a long wait time for the prescribed patients. All real signals are analogue in nature, including brainwaves sensed by EEG systems. For converting the EEG signal into digital for further processing, a truly wearable EEG has to have an analogue mixed-signal front-end (AFE). This research aims to define the specifications for building a custom AFE for the EEG recording and use that to review the suitability of the architectures available in the literature. Another critical task is to provide new architectures that can meet the developed specifications for EEG monitoring and can be used in epilepsy diagnosis, sleep monitoring, drowsiness detection and depression study. The thesis starts with a preview on EEG technology and available methods of brainwaves recording. It further expands to design requirements for the AFE, with a discussion about critical issues that need resolving. Three new continuous-time capacitive feedback chopped amplifier designs are proposed. A novel calibration loop for setting the accurate value for a pseudo-resistor, which is a crucial block in the proposed topology, is also discussed. This pseudoresistor calibration loop achieved the resistor variation of under 8.25%. The thesis also presents a new design of a curvature corrected bandgap, as well as a novel DDA based fourth-order Sallen-Key filter. A modified sensor frontend architecture is then proposed, along with a detailed analysis of its implementation. Measurement results of the AFE are finally presented. The AFE consumed a total power of 3.2A (including ADC, amplifier, filter, and current generation circuitry) with the overall integrated input-referred noise of 0.87V-rms in the frequency band of 0.5-50Hz. Measurement results confirmed that only the proposed AFE achieved all defined specifications for the wearable EEG system with the smallest power consumption than state-of-art architectures that meet few but not all specifications. The AFE also achieved a CMRR of 131.62dB, which is higher than any studied architectures.Open Acces

Ultra-low-power circuits and systems for wearable and implantable medical devices

Thesis (Ph. D.)--Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2013.Cataloged from PDF version of thesis.Includes bibliographical references (pages 219-231).Advances in circuits, sensors, and energy storage elements have opened up many new possibilities in the health industry. In the area of wearable devices, the miniaturization of electronics has spurred the rapid development of wearable vital signs, activity, and fitness monitors. Maximizing the time between battery recharge places stringent requirements on power consumption by the device. For implantable devices, the situation is exacerbated by the fact that energy storage capacity is limited by volume constraints, and frequent battery replacement via surgery is undesirable. In this case, the design of energy-efficient circuits and systems becomes even more crucial. This thesis explores the design of energy-efficient circuits and systems for two medical applications. The first half of the thesis focuses on the design and implementation of an ultra-low-power, mixed-signal front-end for a wearable ECG monitor in a 0.18pm CMOS process. A mixed-signal architecture together with analog circuit optimizations enable ultra-low-voltage operation at 0.6V which provides power savings through voltage scaling, and ensures compatibility with state-of-the-art DSPs. The fully-integrated front-end consumes just 2.9[mu]W, which is two orders of magnitude lower than commercially available parts. The second half of this thesis focuses on ultra-low-power system design and energy-efficient neural stimulation for a proof-of-concept fully-implantable cochlear implant. First, implantable acoustic sensing is demonstrated by sensing the motion of a human cadaveric middle ear with a piezoelectric sensor. Second, alternate energy-efficient electrical stimulation waveforms are investigated to reduce neural stimulation power when compared to the conventional rectangular waveform. The energy-optimal waveform is analyzed using a computational nerve fiber model, and validated with in-vivo ECAP recordings in the auditory nerve of two cats and with psychophysical tests in two human cochlear implant users. Preliminary human subject testing shows that charge and energy savings of 20-30% and 15-35% respectively are possible with alternative waveforms. A system-on-chip comprising the sensor interface, reconfigurable sound processor, and arbitrary-waveform neural stimulator is implemented in a 0.18[mu]m high-voltage CMOS process to demonstrate the feasibility of this system. The sensor interface and sound processor consume just 12[mu]W of power, representing just 2% of the overall system power which is dominated by stimulation. As a result, the energy savings from using alternative stimulation waveforms transfer directly to the system.by Marcus Yip.Ph.D

Noise Analysis and Measurement of Integrator-based Sensor Interface Circuits for Fluorescence Detection in Lab-on-a-chip Applications

Lab-on-a-chip (LOC) biological assays have the potential to fundamentally reform healthcare. The move away from centralized facilities to Point-of-Care (POC) testing of biological assays would improve the speed and accuracy of these, thereby improving patient care. Before LOC can be realized, a number of challenges must be addressed: the need for expert users must be abstracted away; the manufacturing cost of $5 per test threshold must be met; and the supporting infrastructure must be integrated down to an easily portable size. These challenges can be addressed with the deposition of microfluidics on CMOS chips. By designing application specific integrated circuits (ASICs) much of the automation and the supporting infrastructure needed to run these assays can be integrated into the chip. Additionally, CMOS fabrication is some of the most optimized manufacturing in industry today. One of the central challenges with LOC on ASIC is the signal acquisition from the microfluidics into the CMOS. Optical sensing of fluorescence is one form of sensing used for LOC assays. Despite a large literature, there has not been a strong demonstration of monolithic LOC fluorescence detection (FD) for low concentration samples. This work explores the limit-of-detection (LOD) for LOC FD through analysis of the signal and noise of a proposed acquisition channel. The proposed signal acquisition channel consists of an on chip photodiode and integrator based amplification circuits. A hand analysis of the signal propagation through the channel and the noise sources introduced by the circuitry, is performed. This analysis is used to establish relationships between different circuit parameters and the LOD of a hypothetical LOC device. The hand analysis is verified through simulation and the acquisition channel is implemented in: (i) the Austrian Microsystems 350nm CMOS process, (ii) discrete components. Testing of the CMOS chip revealed several issues not identified in extracted simulation; however, the discrete integrator demonstrated many of the trends predicted by the hand analysis and simulations and achieved a LOD of 7.2$\mu M$. This analysis provides insight into the engineering trade-offs required to improve the LOD, to enable more wide spread application of LOC FD

A low-noise transimpedance amplifier for BLM-based ion channel recording

High-throughput screening (HTS) using ion channel recording is a powerful drug discovery technique in pharmacology. Ion channel recording with planar bilayer lipid membranes (BLM) is scalable and has very high sensitivity. A HTS system based on BLM ion channel recording faces three main challenges: (i) design of scalable microfluidic devices; (ii) design of compact ultra-low-noise transimpedance amplifiers able to detect currents in the pA range with bandwidth >10 kHz; (iii) design of compact, robust and scalable systems that integrate these two elements. This paper presents a low-noise transimpedance amplifier with integrated A/D conversion realized in CMOS 0.35 µm technology. The CMOS amplifier acquires currents in the range ±200 pA and ±20 nA, with 100 kHz bandwidth while dissipating 41 mW. An integrated digital offset compensation loop balances any voltage offsets from Ag/AgCl electrodes. The measured open-input input-referred noise current is as low as 4 fA/Root Hz at ±200 pA range. The current amplifier is embedded in an integrated platform, together with a microfluidic device, for current recording from ion channels. Gramicidin-A, alpha-haemolysin and KcsA potassium channels have been used to prove both the platform and the current-to-digital converter

Dopamiinin hapettumisen lukija-anturirajapinta 65 nm CMOS teknologialla

Sensing and monitoring of neural activities within the central nervous system has become a fast-growing area of research due to the need to understand more about how neurons communicate. Several neurological disorders such as Parkinson’s disease, Schizophrenia, Alzeihmers and Epilepsy have been reported to be associated with imbalance in the concentration of neurotransmitters such as glutamate and dopamine [1] - [5]. Hence, this thesis proposes a solution for the measurement of dopamine concentration in the brain during neural communication. The proposed design of the dopamine oxidation readout sensor interface is based on a mixed-signal front-end architecture for minimizing noise and high resolution of detected current signals. The analog front-end is designed for acquisition and amplification of current signals resulting from oxidation and reduction at the biosensor electrodes in the brain. The digital signal processing (DSP) block is used for discretization of detected dopamine oxidation and reduction current signals that can be further processed by an external system. The results from the simulation of the proposed design show that the readout circuit has a current resolution of 100 pA and can detect minimum dopamine concentration of 10 μMol based on measured data from novel diamond-like carbon electrodes [6]. Higher dopamine concentration can be detected from the sensor interface due to its support for a wide current range of 1.2 μA(±600 nA). The digital code representation of the detected dopamine has a resolution of 14.3-bits with RMS conversion error of 0.18 LSB which results in an SNR of 88 dB at full current range input. However, the attained ENOB is 8-bits due to the effect of nonlinearity in the oscillator based ADC. Nonetheless, the achieved resolution of the readout circuit provides good sensitivity of released dopamine in the brain which is useful for further understanding of neurotransmitters and fostering research into improved treatments of related neurodegenerative diseases.Keskushermoston aktiivisuuden havainnointi ja tarkkailu on muodostunut tärkeäksi tutkimusalaksi, sillä tarve ymmärtää neuronien viestintää on kasvanut. Monien hermostollisten sairauksien kuten Parkinsonin taudin, skitsofrenian, Alzheimerin taudin ja epilepsian on huomattu aiheuttavan muutoksia välittäjäaineiden, kuten glutamaatin ja dopamiinin, pitoisuuksissa [1] - [5]. Aiheeseen liittyen tässä työssä esitetään ratkaisu dopamiinipitoisuuden mittaamiseksi aivoista. Esitetty dopamiinipitoisuuden lukijapiiri perustuu sekamuotoiseen etupäärakenteeseen, jolla saavutetaan matala kohinataso ja hyvä tarkkuus signaalien ilmaisemisessa. Suunniteltu analoginen etupää kykenee lukemaan ja vahvistamaan dopamiinipitoisuuden muutosten aiheuttamia virran muutoksia aivoihin asennetuista elektrodeista. Digitaalisen signaalinkäsittelyn avulla voidaan havaita dopamiinin hapettumis-ja pelkistymisvirtasignaalit, ja välittää ne edelleen ulkoisen järjestelmän muokattavaksi. Simulaatiotulokset osoittavat, että suunniteltu piiri saavuttaa 100 pA virran erottelukyvyn. Simuloinnin perustuessa hiilipohjaisiin dopamiinielektrodeihin piiri voi havaita 10 μMol dopamiinipitoisuuden [6]. Myös suurempia dopamiinipitoisuuksia voidaan havaita, sillä etupäärajapinta tukee 1.2 μA(±600 nA) virta-aluetta. Digitaalinen esitysmuoto tukee 14.3 bitin esitystarkkuutta 0.18 bitin RMS virheellä saavuttaen 88 dB dynaamisen virta-alueen. Saavutettu ENOB (tehollinen bittimäärä) on kuitenkin 8 bittiä oskillaattoripohjaisen ADC:n (analogia-digitaalimuuntimen) epälineaarisuuden takia. Saavutettu tarkkuus tuottaa hyvän herkkyyden dopamiinin havaitsemiseksi ja hyödyttää siten välittäjäainetutkimusta ja uusien hoitomuotojen kehittämistä hermostollisiin sairauksiin

High-speed Time-interleaved Digital-to-Analog Converter (TI-DAC) for Self-Interference Cancellation Applications

Nowadays, the need for higher data-rate is constantly growing to enhance the quality of the daily communication services. The full-duplex (FD) communication is exemplary method doubling the data-rate compared to half-duplex one. However, part of the strong output signal of the transmitter interferes to the receiver-side because they share the same antenna with limited attenuation and, as a result, the receiver’s performance is corrupted. Hence, it is critical to remove the leakage signal from the receiver’s path by designing another block called self-interference cancellation (SIC). The main goal of this dissertation is to develop the SIC block embedded in the current-mode FD receivers. To this end, the regenerated cancellation current signal is fed to the inputs of the base-band filter and after the mixer of a (direct-conversion) current-mode FD receiver. Since the pattern of the transmitter (the digital signal generated by DSP) is known, a high-speed digital-to-Analog converter (DAC) with medium-resolution can perfectly suppress main part of the leakage on the receiver path. A capacitive DAC (CDAC) is chosen among the available solutions because it is compatible with advanced CMOS technology for high-speed application and the medium-resolution designs. Although the main application of the design is to perform the cancellation, it can also be employed as a stand-alone DAC in the Analog (I/Q) transmitter. The SIC circuitry includes a trans-impedance amplifier (TIA), two DACs, high-speed digital circuits, and built-in-self-test section (BIST). According to the available specification for full-duplex communication system, the resolution and working frequency of the CDAC are calculated (designed) equal to 10-bit (3 binary+ 2 binary + 5 thermometric) and 1GHz, respectively. In order to relax the design of the TIA (settling time of the DAC), the CDAC implements using 2-way time-interleaved (TI) manner (the effective SIC frequency equals 2GHz) without using any calibration technique. The CDAC is also developed with the split-capacitor technique to lower the negative effects of the conventional binary-weighted DAC. By adding one extra capacitor on the left-side of the split-capacitor, LSB-side, the value of the split-capacitor can be chosen as an integer value of the unit capacitor. As a result, it largely enhances the linearity of the CADC and cancellation performance. If the block works as a stand-alone DAC with non-TI mode, the digital input code representing a Sinus waveform with an amplitude 1dB less than full-scale and output frequency around 10.74MHz, chosen by coherent sampling rule, then the ENOB, SINAD, SFDR, and output signal are 9.4-bit, 58.2 dB, 68.4dBc, and -9dBV. The simulated value of the |DNL| (static linearity) is also less than 0.7. The similar simulation was done in the SIC mode while the capacitive-array woks in the TI mode and cancellation current is set to the full-scale. Hence, the amount of cancelling the SI signal at the output of the TIA, SNDR, SFDR, SNDRequ. equals 51.3dB, 15.1 dB, 24dBc, 66.4 dB. The designed SIC cannot work as a closed-loop design. The layout was optimally drawn in order to minimize non-linearity, the power-consumption of the decoders, and reduce the complexity of the DAC. By distributing the thermometric cells across the array and using symmetrical switching scheme, the DAC is less subjected to the linear and gradient effect of the oxide. Based on the post-layout simulation results, the deviation of the design after drawing the layout is studied. To compare the results of the schematic and post-layout designs, the exact conditions of simulation above (schematic simulations) are used. When the block works as a stand-alone CDAC, the ENOB, SINAD, SFDR are 8.5-bit, 52.6 dB, 61.3 dBc. The simulated value of the |DNL| (static linearity) is also limited to 1.3. Likewise, the SI signal at the output of the TIA, SNDR, SFDR, SNDRequ. are equal to 44dB, 11.7 dB, 19 dBc, 55.7 dB