A Built-In-Test Circuit for Functional Verification & PVT Variations Monitoring of CMOS RF Circuits

Built-In-Test (BIT) for Radio Frequency (RF) integrated circuits can reduce the testing cost, especially with the increase of integration level and operating frequency. A fully integrated CMOS BIT detection circuit is presented in this work. This BIT detection circuit is rectifier-based and low threshold voltage diode-connected MOS transistor with substrate positively-biased is used to improve the detecting sensitivity. As an example, a 2.4GHz LNA is used, the high frequency small signal gain is extracted and the gain fluctuation due to Process, supply Voltage and Temperature (PVT) variations is also investigated. The simulation results show that this BIT detection circuit can realize on-chip functional verification of RF circuits and also monitor the influence of PVT variations on the performance of the circuit without affecting the high frequency performance of the measured RF circuits

Spectral Signature Analysis – BIST for RF Front-Ends

In this paper, the Spectral Signature Analysis is presented as a concept for an integrable self-test system (Built-In Self-Test – BIST) for RF front-ends is presented. It is based on modelling the whole RF front-end (transmitter and receiver) on system level, on generating of a Spectral Signature and of evaluating of the Signature Response. Because of using multi-carrier signal as the test signature, the concept is especially useful for tests of linearity and frequency response of front-ends. Due to the presented method of signature response evaluation, this concept can be used for Built-In Self-Correction (BISC) at critical building blocks

On-the-fly Computation Method in Field-Programmable Gate Array for Analog-to-Digital Converter Linearity Testing

This paper presents a new approach to linearity testing of analog-to-digital converters (ADCs) through on-the-fly computation in field-programmable gate array (FPGA) hardware. The proposed method computes the linearity while it is processing without compromising the accuracy of the measurement, so very little overhead time is required to compute the final linearity. The results will be displayed immediately after a single ramp is supplied to the device under test. This is a cost-effective chip testing solution for semiconductor companies, achieved by reducing computing time and utilization of low-cost and low-specification automatic test equipment (ATE). The experimental results showed that the on-the-fly computation method significantly reduced the computation time (up to 44.4%) compared to the conventional process. Thus, for every 100M 12-bit ADC tested with 32 hits per code, the company can save up to 139,972 Php on electricity consumption

On-the-fly computation method in field-programmable gate array for analog-to-digital converter linearity testing

© 2018 Published by ITB Journal Publisher. This paper presents a new approach to linearity testing of analog-to-digital converters (ADCs) through on-the-fly computation in field-programmable gate array (FPGA) hardware. The proposed method computes the linearity while it is processing without compromising the accuracy of the measurement, so very little overhead time is required to compute the final linearity. The results will be displayed immediately after a single ramp is supplied to the device under test. This is a cost-effective chip testing solution for semiconductor companies, achieved by reducing computing time and utilization of low-cost and low-specification automatic test equipment (ATE). The experimental results showed that the on-the-fly computation method significantly reduced the computation time (up to 44.4%) compared to the conventional process. Thus, for every 100M 12-bit ADC tested with 32 hits per code, the company can save up to 139,972 Php on electricity consumption

Built-In Self-Test for Automatic Analog Frequency Response Measurement

Abstract-We present a Built-In Self-Test (BIST) approach based on direct digital synthesizer (DDS) for functional test of analog circuitry in mixed-signal systems. DDS with delta-sigma noise shaping is used to generate test signals with different frequencies and phases. The DDS-based BIST hardware implementation can sweep the frequencies through the interested bands and thus measure the frequency response of the analog circuit. The proposed BIST approach has been implemented in Verilog and synthesized into a Field Programmable Gate Array (FPGA). The actual device under test (DUT) was implemented using a Field Programmable Analog Array (FPAA) to form a complete BIST testbed for analog functional tests

Accurate Jitter Decomposition in High-Speed Links

In a high-speed digital communication system, jitter performance plays a crucial role in Bit-Error Rate (BER). It is important to accurately derive each type of jitter as well as total jitter (TJ) and to identify the root causes of jitter by jitter decomposition. In this work, we propose new jitter decomposition techniques in high-speed links testing. The background of jitter decomposition is described in chapter 1. In chapter 2, duty cycle distortion jitter amplification is introduced. As channel loss results in both ISI and jitter amplification, DCD amplification is a big concern in high-speed links. The derivation of a formula of DCD amplification for data channels is included and the calculation result matches the time-domain simulation in the system. Chapter 3 provides an accurate jitter decomposition algorithm using Least Squares (LS) which simultaneously separates ISI, RJ, and PJ. A new time domain ISI model is proposed, which is faster and more accurate than the conventional ISI model. This algorithm obtains the estimated individual jitter component value with fine accuracy by using less samples of total jitter data compared with conventional methods. The simulation and measurement show the accuracy and efficiency of this algorithm with less data samples. In chapter 4, a low-cost comparator-based jitter decomposition algorithm is proposed. Instead of using TIE jitter sequence to decompose, it uses a low cost and simple comparator network to identify the deviation of current sampling positions from the ideal sampling positions to represent the TIE. It simultaneously separates ISI, DCD, and PJ and can achieve similar accuracy compared to the instrument test. Both the simulation and measurement show the decomposition algorithm with great accuracy and efficiency. In chapter 5, a low cost and simple dithering method to improve the test of linearity of analog-to-digital converter (ADC) is proposed. This method exhibits an improvement and enhancement for the ultra-fast segmented model identification of linearity error (uSMILE) algorithm which reduces 99% of the test time compared to the conventional method. In this study, we proposed three types of distribution dithering methods adding to the ramp input signal to reduce the estimation error when uSMILE was applied in low resolution ADCs. The fix pattern distribution was proved as the most efficient and cost-effective method by comparing with the Gaussian, uniform, and fix-pattern distributions. Both the simulation results and hardware measurement indicate that the estimation error can be significantly reduced in 12-bit SAR ADC with effective dithering

Methodology for testing high-performance data converters using low-accuracy instruments

There has been explosive growth in the consumer electronics market during the last decade. As the IC industry is shifting from PC-centric to consumer electronics-centric, digital technologies are no longer solving all the problems. Electronic devices integrating mixed-signal, RF and other non-purely digital functions are becoming new challenges to the industry. When digital testing has been studied for long time, testing of analog and mixed-signal circuits is still in its development stage. Existing solutions have two major problems. First, high-performance mixed-signal test equipments are expensive and it is difficult to integrate their functions on chip. Second, it is challenging to improve the test capability of existing methods to keep up with the fast-evolving performance of mixed-signal products demanded on the market. The International Technology Roadmap for Semiconductors identified mixed-signal testing as one of the most daunting system-on-a-chip challenges;My works have been focused on developing new strategies for testing the analog-to-digital converter (ADC) and digital-to-analog converter (DAC). Different from conventional methods that require test instruments to have better performance than the device under test, our algorithms allow the use of medium and low-accuracy instruments in testing. Therefore, we can provide practical and accurate test solutions for high-performance data converters. Meanwhile, the test cost is dramatically reduced because of the low price of such test instruments. These algorithms have the potential for built-in self-test and can be generalized to other mixed-signal circuitries. When incorporated with self-calibration, these algorithms can enable new design techniques for mixed-signal integrated circuits. Following contents are covered in the dissertation:;(1) A general stimulus error identification and removal (SEIR) algorithm that can test high-resolution ADCs using two low-linearity signals with a constant offset in between; (2) A center-symmetric interleaving (CSI) strategy for generating test signals to be used with the SEIR algorithm; (3) An architecture-based test algorithm for high-performance pipelined or cyclic ADCs using a single nonlinear stimulus; (4) Using Kalman Filter to improve the efficiency of ADC testing; and (5) A testing algorithm for high-speed high-resolution DACs using low-resolution ADCs with dithering

Programmable CMOS Analog-to-Digital Converter Design and Testability

In this work, a programmable second order oversampling CMOS delta-sigma analog-to-digital converter (ADC) design in 0.5µm n-well CMOS processes is presented for integration in sensor nodes for wireless sensor networks. The digital cascaded integrator comb (CIC) decimation filter is designed to operate at three different oversampling ratios of 16, 32 and 64 to give three different resolutions of 9, 12 and 14 bits, respectively which impact the power consumption of the sensor nodes. Since the major part of power consumed in the CIC decimator is by the integrators, an alternate design is introduced by inserting coder circuits and reusing the same integrators for different resolutions and oversampling ratios to reduce power consumption. The measured peak signal-to-noise ratio (SNR) for the designed second order delta-sigma modulator is 75.6dB at an oversampling ratio of 64, 62.3dB at an oversampling ratio of 32 and 45.3dB at an oversampling ratio of 16. The implementation of a built-in current sensor (BICS) which takes into account the increased background current of defect-free circuits and the effects of process variation on ΔIDDQ testing of CMOS data converters is also presented. The BICS uses frequency as the output for fault detection in CUT. A fault is detected when the output frequency deviates more than ±10% from the reference frequency. The output frequencies of the BICS for various model parameters are simulated to check for the effect of process variation on the frequency deviation. A design for on-chip testability of CMOS ADC by linear ramp histogram technique using synchronous counter as register in code detection unit (CDU) is also presented. A brief overview of the histogram technique, the formulae used to calculate the ADC parameters, the design implemented in 0.5µm n-well CMOS process, the results and effectiveness of the design are described. Registers in this design are replaced by 6T-SRAM cells and a hardware optimized on-chip testability of CMOS ADC by linear ramp histogram technique using 6T-SRAM as register in CDU is presented. The on-chip linear ramp histogram technique can be seamlessly combined with ΔIDDQ technique for improved testability, increased fault coverage and reliable operation