Analysis and design on low-power multi-Gb/s serial links

High speed serial links are critical components for addressing the growing demand for I/O bandwidth in next-generation computing applications, such as many-core systems, backplane and optical data communications. Due to continued process scaling and circuit innovations, today's CMOS serial link transceivers can achieve tens of Gb/s per pin. However, most of their reported power efficiency improves much slower than the rise of data rate. Therefore, aggregate I/O power is increasing and will exceed the power budget if the trend for more off-chip bandwidth is sustained. In this work, a system level statistical analysis of serial links is first described, and compares the link performance of Non-Return-to-Zero (2-PAM) with higher-order modulation (duobinary) signaling schemes. This method enables fast and accurate BER distribution simulation of serial link transceivers that include channel and circuit imperfections, such as finite pulse rise/fall time, duty cycle variation, and both receiver and transmitter forwarded-clock jitter. Second, in order to address link power efficiency, two test chips have been implemented. The first one describes a quad-lane, 6.4-7.2 Gb/s serial link receiver prototype using a forwarded clock architecture. A novel phase deskew scheme using injection-locked ring oscillators (ILRO) is proposed that achieves greater than one UI of phase shift for multiple clock phases, eliminating phase rotation and interpolation required in conventional architectures. Each receiver, optimized for power efficiency, consists of a low-power linear equalizer, four offset-cancelled quantizers for 1:4 demultiplexing, and an injection-locked ring oscillator coupled to a low-voltage swing, global clock distribution. Measurement results show a 6.4-7.2Gb/s data rate with BER < 10⁻¹² across 14 cm of PCB, and an 8Gb/s data rate through 4cm of PCB. Designed in a 1.2V, 90nm CMOS process, the ILRO achieves a wide tuning range from 1.6-2.6GHz. The total area of each receiver is 0.0174mm², resulting in a measured power efficiency of 0.6mW/Gb/s. Improving upon the first test chip, a second test chip for 8Gb/s forwarded clock serial link receivers exploits a low-power super-harmonic injection-locked ring oscillator for symmetric multi-phase local clock generation and deskewing. Further power reduction is achieved by designing most of the receiver circuits in the near-threshold region (0.6V supply), with the exception of only the global clock buffer, test buffers and synthesized digital test circuits at nominal 1V supply. At the architectural level, a 1:10 direct demultiplexing rate is chosen to achieve low supply operation by exploiting high-parallelism. Fabricated in 65nm CMOS technology, two receiver prototypes are integrated in this test chip, one without and the other with front-end boot-strapped S/Hs. Including the amortized power of global clock distribution, the proposed serial link receivers consume 1.3mW and 2mW respectively at 8Gb/s input data rate, achieving a power efficiency of 0.163mW/Gb/s and 0.25mW/Gb/s. Measurement results show both receivers achieve BER < 10⁻¹² across a 20-cm FR4 PCB channel

COSMIC: An Ethernet-based Commensal, Multimode Digital Backend on the Karl G. Jansky Very Large Array for the Search for Extraterrestrial Intelligence

The primary goal of the search for extraterrestrial intelligence (SETI) is to gain an understanding of the prevalence of technologically advanced beings (organic or inorganic) in the Galaxy. One way to approach this is to look for technosignatures: remotely detectable indicators of technology, such as temporal or spectral electromagnetic emissions consistent with an artificial source. With the new Commensal Open-Source Multimode Interferometer Cluster (COSMIC) digital backend on the Karl G. Jansky Very Large Array (VLA), we aim to conduct a search for technosignatures that is significantly more comprehensive, more sensitive, and more efficient than previously attempted. The COSMIC system is currently operational on the VLA, recording data, and designed with the flexibility to provide user-requested modes. This paper describes the hardware system design, the current software pipeline, and plans for future development.Comment: 30 pages, 17 figures. Accepted for publication in A

Secure Communication in Disaster Scenarios

Während Naturkatastrophen oder terroristischer Anschläge ist die bestehende Kommunikationsinfrastruktur häufig überlastet oder fällt komplett aus. In diesen Situationen können mobile Geräte mithilfe von drahtloser ad-hoc- und unterbrechungstoleranter Vernetzung miteinander verbunden werden, um ein Notfall-Kommunikationssystem für Zivilisten und Rettungsdienste einzurichten. Falls verfügbar, kann eine Verbindung zu Cloud-Diensten im Internet eine wertvolle Hilfe im Krisen- und Katastrophenmanagement sein. Solche Kommunikationssysteme bergen jedoch ernsthafte Sicherheitsrisiken, da Angreifer versuchen könnten, vertrauliche Daten zu stehlen, gefälschte Benachrichtigungen von Notfalldiensten einzuspeisen oder Denial-of-Service (DoS) Angriffe durchzuführen. Diese Dissertation schlägt neue Ansätze zur Kommunikation in Notfallnetzen von mobilen Geräten vor, die von der Kommunikation zwischen Mobilfunkgeräten bis zu Cloud-Diensten auf Servern im Internet reichen. Durch die Nutzung dieser Ansätze werden die Sicherheit der Geräte-zu-Geräte-Kommunikation, die Sicherheit von Notfall-Apps auf mobilen Geräten und die Sicherheit von Server-Systemen für Cloud-Dienste verbessert

Parallel reconfigurable single photon avalanche diode array for optical communications

There is a pressing need to develop alternative communications links due to a number of physical phenomena, limiting the bandwidth and energy efficiency of wire-based systems or economic factors such as cost, material-supply reliability and environmental costs. Networks have moved to optical connections to reduce costs, energy use and to supply high data rates. A primary concern is that current optical-detection devices require high optical power to achieve fast data rates with high signal quality. The energy required therefore, quickly becomes a problem. In this thesis, advances in single-photon avalanche diodes (SPADs) are utilised to reduce the amount of light needed and to reduce the overall energy budget. Current high performance receivers often use exotic materials, many of which have severe environmental impact and have cost, supply and political restrictions. These present a problem when it comes to integration; hence silicon technology is used, allowing small, mass-producible, low power receivers. A reconfigurable SPAD-based integrating receiver in standard 130nm imaging CMOS is presented for links with a readout bandwidth of 100MHz. A maximum count rate of 58G photon/s is observed, with a dynamic range of ≈ 79dB, a sensitivity of ≈ −31.7dBm at 100MHz and a BER of ≈ 1x10−9. We investigate the properties of the receiver for optical communications in the visible spectrum, using its added functionality and reconfigurability to experimentally explore non-ideal influences. The all-digital 32x32 SPAD array, achieves a minimum dead time of 5.9ns, and a median dark count rate (DCR) of 2.5kHz per SPAD. High noise devices can be weighted or removed to optimise the SNR. The power requirements, transient response and received data are explored and limiting factors similar to those of photodiode receivers are observed. The thesis concludes that data can be captured well with such a device but more electrical energy is needed at the receiver due to its fundamental operation. Overall, optical power can be reduced, allowing significant savings in either transmitter power or the transmission length, along with the advantages of an integrated digital chip