A 1.2 V and 69 mW 60 GHz Multi-channel Tunable CMOS Receiver Design

A multi-channel receiver operating between 56 GHz and 70 GHz for coverage of different 60 GHz bands worldwide is implemented with a 90 nm Complementary Metal-Oxide Semiconductor (CMOS) process. The receiver containing an LNA, a frequency down-conversion mixer and a variable gain amplifier incorporating a band-pass filter is designed and implemented. This integrated receiver is tested at four channels of centre frequencies 58.3 GHz, 60.5 GHz, 62.6 GHz and 64.8 GHz, employing a frequency plan of an 8 GHz-intermediate frequency (IF). The achieved conversion gain by coarse gain control is between 4.8 dB–54.9 dB. The millimeter-wave receiver circuit is biased with a 1.2V supply voltage. The measured power consumption is 69 mW

Crystal-Less RF Communication Integrated Circuits for Wireless Sensor Networks.

The evolution of computing devices has changed daily life significantly over the past decades, and it is still advancing towards pervasive and ubiquitous networks. At each step, the volume shrinks by 2-3 orders of magnitude while the functionality and computing power remains constant or increases. Wireless sensor networks (WSN) are perceived as the next big step of computing technology for a variety of applications, including environmental sensing, health monitoring, un-obtrusive surveillance and invisible labeling. With thin-film micro-battery technology and CMOS scaling, we can now envision complete sensor nodes with cubic-mm form factors. As node volume reduces, external components like a crystal frequency reference, which does not scale with frequency or process, becomes one of the bottlenecks of realizing cubic-mm WSN node devices. This dissertation covers several aspects of the energy and integration challenges associated with cubic-mm WSN nodes without crystal references. Several new compact and low-power RF circuits for the synchronization and communication of WSN nodes are proposed and discussed. A 60GHz antenna-referenced frequency-locked loop (FLL) using an on-chip patch antenna as both the radiator and the frequency reference has been demonstrated for RF synchronization. The FLL, targeting communication of non-coherent energy detection systems, provides adequate frequency accuracy without crystal references. A 10GHz ultra-wideband (UWB) crystal-less transmitter with an on-chip monopole antenna has also been demonstrated. It operates over the supply voltage range of a micro-battery; generate tunable pulse durations and center frequencies, and lives on an on-chip local decoupling capacitor only. A 1MHz temperature-compensated relaxation oscillator is also proposed in the dissertation for baseband data synchronization. With the modified RC network of the conventional relaxation oscillator, the transfer function of the network has a transmission zero, introducing an additional degree-of-freedom for temperature compensation design. Finally, a 60GHz transmit/receive (T/R) switch-less antenna front-end using an on-chip patch antenna is presented, which has an in-band isolation inherited from the standing wave pattern without implementing a T/R switch. The research projects have explored the circuit design techniques and system integration for cubic-mm energy-constrained devices, achieving both long lifetimes and small volumes for WSN applications.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/99763/1/kkhuang_1.pd

Design and characterization of monolithic millimeter-wave active and passive components, low-noise and power amplifiers, resistive mixers, and radio front-ends

This thesis focuses on the design and characterization of monolithic active and passive components, low-noise and power amplifiers, resistive mixers, and radio front-ends for millimeter-wave applications. The thesis consists of 11 publications and an overview of the research area, which also summarizes the main results of the work. In the design of millimeter-wave active and passive components the main focus is on realized CMOS components and techniques for pushing nanoscale CMOS circuits beyond 100 GHz. Test structures for measuring and analyzing these components are shown. Topologies for a coplanar waveguide, microstrip line, and slow-wave coplanar waveguide that are suitable for implementing transmission lines in nanoscale CMOS are presented. It is demonstrated that the proposed slow-wave coplanar waveguide improves the performance of the transistor-matching networks when compared to a conventional coplanar waveguide and the floating slow-wave shield reduces losses and simplifies modeling when extended below other passives, such as DC decoupling and RF short-circuiting capacitors. Furthermore, wideband spiral transmission line baluns in CMOS at millimeter-wave frequencies are demonstrated. The design of amplifiers and a wideband resistive mixer utilizing the developed components in 65-nm CMOS are shown. A 40-GHz amplifier achieved a +6-dBm 1-dB output compression point and a saturated output power of 9.6 dBm with a miniature chip size of 0.286 mm². The measured noise figure and gain of the 60-GHz amplifier were 5.6 dB and 11.5 dB, respectively. The V-band balanced resistive mixer achieved a 13.5-dB upconversion loss and 34-dB LO-to-RF isolation with a chip area of 0.47 mm². In downconversion, the measured conversion loss and 1-dB input compression point were 12.5 dB and +5 dBm, respectively. The design and experimental results of low-noise and power amplifiers are presented. Two wideband low-noise amplifiers were implemented in a 100-nm metamorphic high electron mobility transistor (HEMT) technology. The amplifiers achieved a 22.5-dB gain and a 3.3-dB noise figure at 94 GHz and a 18-19-dB gain and a 5.5-7.0-dB noise figure from 130 to 154 GHz. A 60-GHz power amplifier implemented in a 150-nm pseudomorphic HEMT technology exhibited a +17-dBm 1-dB output compression point with a 13.4-dB linear gain. In this thesis, the main system-level aspects of millimeter-wave transmitters and receivers are discussed and the experimental circuits of a 60-GHz transmitter front-end and a 60-GHz receiver with an on-chip analog-to-digital converter implemented in 65-nm CMOS are shown. The receiver exhibited a 7-dB noise figure, while the saturated output power of the transmitter front-end was +2 dBm. Furthermore, a wideband W-band transmitter front-end with an output power of +6.6 dBm suitable for both image-rejecting superheterodyne and direct-conversion transmission is demonstrated in 65-nm CMOS

Design methods for 60GHz beamformers in CMOS

The 60GHz band is promising for applications such as high-speed short-range wireless personal-area network (WPAN), real-time video streaming at rates of several-Gbps, automotive radar, and mm-Wave imaging, since it provides a large amount of bandwidth that can freely (i.e. without a license) be used worldwide. However, transceivers at 60GHz pose several additional challenges over microwave transceivers. In addition to the circuit design challenges of implementing high performance 60GHz RF circuits in mainstream CMOS technology, the path loss at 60GHz is significantly higher than at microwave frequencies because of the smaller size of isotropic antennas. This can be overcome by using phased array technology. This thesis studies the new concepts and design techniques that can be used for 60GHz phased array systems. It starts with an overview of various applications at mm-wave frequencies, such as multi-Gbps radio at 60GHz, automotive radar and millimeter-wave imaging. System considerations of mm-wave receivers and transmitters are discussed, followed by the selection of a CMOS technology to implement millimeter-wave (60GHz) systems. The link budget of a 60GHz WPAN is analyzed, which leads to the introduction of phased array techniques to improve system performance. Different phased array architectures are studied and compared. The system requirements of phase shifters are discussed. Several types of conventional RF phase shifters are reviewed. A 60GHz 4-bit passive phase shifter is designed and implemented in a 65nm CMOS technology. Measurement results are presented and compared to published prior art. A 60GHz 4-bit active phase shifter is designed and integrated with low noise amplifier and combiner for a phased array receiver. This is implemented in a 65nm CMOS technology, and the measurement results are presented. The design of a 60GHz 4-bit active phase shifter and its integration with power amplifier is also presented for a phased array transmitter. This is implemented in a 65nm CMOS technology. The measurement results are also presented and compared to reported prior art. The integration of a 60GHz CMOS amplifier and an antenna in a printed circuit-board (PCB) package is investigated. Experimental results are presented and discussed

A Research on High-Performance Analog-to-Digital Converters in Wireless Communication Systems

博士(工学)法政大学 (Hosei University

Energy-efficient, short-range ultra-wideband radio transceivers

Short-range wireless communications continually attract interest from both industry and academia, and it is changing our life in every aspect in the last decade. The design of wireless transceivers is the bottleneck for variety applications, due to RF modeling inaccuracy, stringent FCC regulations over the transmitted power spectrum, interference, multi-path reflections, modulation scheme, receiver sensitivity, and synchronization. In addition, energy efficiency is always one of the most important design goals. Ultra-Wideband(UWB) is found to be very energy-efficient due to its low duty cycle and potentially high data rate due to its wide bandwidth. However, there still remain unsolved issues with UWB transceivers, such as pulse shaping, multi-path reflections, and receiver clock synchronization. To address these, novel techniques such as wireless multi-path equalization, pulse injection-locking for receiver clock synchronization, reconfigurable pulse shaping, low power wireless clock distribution, and an ultra-low-power super-regenerative receiver are implemented and verified on silicon. Three chips are designed and verified: a 3-5GHz Impulse-Radio(IR) UWB transceiver, a 3-60GHz all digital reconfigurable transmitter, and a 402-405MHz MICS/UWB(Sub-GHz) super-regenerative receiver incorporating wireless clock synchronization. A detailed design methodology, measurement results, and discussions are presented

Energy-Efficient Wireless Circuits and Systems for Internet of Things

As the demand of ultra-low power (ULP) systems for internet of thing (IoT) applications has been increasing, large efforts on evolving a new computing class is actively ongoing. The evolution of the new computing class, however, faced challenges due to hard constraints on the RF systems. Significant efforts on reducing power of power-hungry wireless radios have been done. The ULP radios, however, are mostly not standard compliant which poses a challenge to wide spread adoption. Being compliant with the WiFi network protocol can maximize an ULP radio’s potential of utilization, however, this standard demands excessive power consumption of over 10mW, that is hardly compatible with in ULP systems even with heavy duty-cycling. Also, lots of efforts to minimize off-chip components in ULP IoT device have been done, however, still not enough for practical usage without a clean external reference, therefore, this limits scaling on cost and form-factor of the new computer class of IoT applications. This research is motivated by those challenges on the RF systems, and each work focuses on radio designs for IoT applications in various aspects. First, the research covers several endeavors for relieving energy constraints on RF systems by utilizing existing network protocols that eventually meets both low-active power, and widespread adoption. This includes novel approaches on 802.11 communication with articulate iterations on low-power RF systems. The research presents three prototypes as power-efficient WiFi wake-up receivers, which bridges the gap between industry standard radios and ULP IoT radios. The proposed WiFi wake-up receivers operate with low power consumption and remain compatible with the WiFi protocol by using back-channel communication. Back-channel communication embeds a signal into a WiFi compliant transmission changing the firmware in the access point, or more specifically just the data in the payload of the WiFi packet. With a specific sequence of data in the packet, the transmitter can output a signal that mimics a modulation that is more conducive for ULP receivers, such as OOK and FSK. In this work, low power mixer-first receivers, and the first fully integrated ultra-low voltage receiver are presented, that are compatible with WiFi through back-channel communication. Another main contribution of this work is in relieving the integration challenge of IoT devices by removing the need for external, or off-chip crystals and antennas. This enables a small form-factor on the order of mm3-scale, useful for medical research and ubiquitous sensing applications. A crystal-less small form factor fully integrated 60GHz transceiver with on-chip 12-channel frequency reference, and good peak gain dual-mode on-chip antenna is presented.PHDElectrical and Computer EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/162975/1/jaeim_1.pd

Analog/RF Circuit Design Techniques for Nanometerscale IC Technologies

CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds conventional matching tolerances requiring active cancellation techniques or alternative architectures. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin- and thick-oxide transistors. Alternatively, low voltage circuit techniques are successfully developed. In order to benefit from nanometer scale CMOS technology, more functionality is shifted to the digital domain, including parts of the RF circuits. At the same time, analog control for digital and digital control for analog emerges to deal with current and upcoming imperfections