Energy-efficient, short-range ultra-wideband radio transceivers

Short-range wireless communications continually attract interest from both industry and academia, and it is changing our life in every aspect in the last decade. The design of wireless transceivers is the bottleneck for variety applications, due to RF modeling inaccuracy, stringent FCC regulations over the transmitted power spectrum, interference, multi-path reflections, modulation scheme, receiver sensitivity, and synchronization. In addition, energy efficiency is always one of the most important design goals. Ultra-Wideband(UWB) is found to be very energy-efficient due to its low duty cycle and potentially high data rate due to its wide bandwidth. However, there still remain unsolved issues with UWB transceivers, such as pulse shaping, multi-path reflections, and receiver clock synchronization. To address these, novel techniques such as wireless multi-path equalization, pulse injection-locking for receiver clock synchronization, reconfigurable pulse shaping, low power wireless clock distribution, and an ultra-low-power super-regenerative receiver are implemented and verified on silicon. Three chips are designed and verified: a 3-5GHz Impulse-Radio(IR) UWB transceiver, a 3-60GHz all digital reconfigurable transmitter, and a 402-405MHz MICS/UWB(Sub-GHz) super-regenerative receiver incorporating wireless clock synchronization. A detailed design methodology, measurement results, and discussions are presented

The Design of Low Power Ultra-Wideband Transceiver

Ph.DDOCTOR OF PHILOSOPH

Power-efficient Circuit Architectures for Receivers Leveraging Nanoscale CMOS

Cellular and mobile communication markets, together with CMOS technology scaling, have made complex systems-on-chip integrated circuits (ICs) ubiquitous. Moving towards the internet of things that aims to extend this further requires ultra-low power and efficient radio communication that continues to take advantage of nanoscale CMOS processes. At the heart of this lie orthogonal challenges in both system and circuit architectures of current day technology. By enabling transceivers at center frequencies ranging in several tens of GHz, modern CMOS processes support bandwidths of up to several GHz. However, conventional narrowband architectures cannot directly translate or trade-off these speeds to lower power consumption. Pulse-radio UWB (PR-UWB), a fundamentally different system of communication enables this trade-off by bit-level duty-cycling i.e., power-gating and has emerged as an alternative to conventional narrowband systems to achieve better energy efficiency. However, system-level challenges in the implementation of transceiver synchronization and duty-cycling have remained an open challenge to realize the ultra-low power numbers that PR-UWB promises. Orthogonally, as CMOS scaling continues, approaching 28nm and 14nm in production digital processes, the key transistor characteristics have rapidly changed. Changes in supply voltage, intrinsic gain and switching speeds have rendered conventional analog circuit design techniques obsolete, since they do not scale well with the digital backend engines that dictate scaling. Consequently, circuit architectures that employ time-domain processing and leverage the faster switching speeds have become attractive. However, they are fundamentally limited by their inability to support linear domain-to-domain conversion and hence, have remained un-suited to high-performance applications. Addressing these requirements in different dimensions, two pulse-radio UWB receiver and a continuous-time filter silicon prototypes are presented in this work. The receiver prototypes focus on system level innovation while the filter serves as a demonstration vehicle for novel circuit architectures developed in this work. The PR-UWB receiver prototypes are implemented in a 65nm LP CMOS technology and are fully integrated solutions. The first receiver prototype is a compact UWB receiver front end operating at 4.85GHz that is aggressively duty-cycled. It occupies an active area of only 0.4 mm², thanks to the use of few inductors and RF G_m-C filters and incorporates an automatic-threshold-recovery-based demodulator for digitization. The prototype achieves a sensitivity of -88dBm at a data rate of 1Mbps (for a BER of 10^-3), while achieving the lowest energy consumption gradient (dP/df_data=450pJ/bit) amongst other receivers operating in the lower UWB band, for the same sensitivity. However, this prototype is limited by idle-time power consumption (e.g., bias) and lacks synchronization capability. A fully self-duty-cycled and synchronized UWB pulse-radio receiver SoC targeted at low-data-rate communication is presented as the second prototype. The proposed architecture builds on the automatic-threshold-recovery-based demodulator to achieve synchronization using an all-digital clock and data recovery loop. The SoC synchronizes with the incoming pulse stream from the transmitter and duty-cycles itself. The SoC prototype achieves a -79.5dBm, 1Mbps-normalized sensitivity for a >5X improvement over the state of the art in power consumption (375pJ/bit), thanks to aggressive signal path and bias circuit duty-cycling. The SoC is fully integrated to achieve RF-in to bit-out operation and can interface with off-chip, low speed digital components. Finally, switched-mode signal processing, a signal processing paradigm that enables the design of highly linear, power-efficient feedback amplifiers is presented. A 0.6V continuous-time filter prototype that demonstrates the advantages of this technique is presented in a 65nm GP CMOS process. The filter draws 26.2mW from the supply while operating at a full-scale that is 73% of the V_dd, a bandwidth of 70MHz and a peak signal-to-noise-and-distortion ratio (SNDR) of 55.8dB. This represents a 2-fold improvement in full-scale and a 10-fold improvement in the bandwidth over state-of-the-art filter implementations, while demonstrating excellent linearity and signal-to-noise ratio. To sum up, innovations spanning both system and circuit architectures that leverage the speeds of nanoscale CMOS processes to enable power-efficient solutions to next-generation wireless receivers are presented in this work

Wireless Testing of Integrated Circuits.

Integrated circuits (ICs) are usually tested during manufacture by means of automatic testing equipment (ATE) employing probe cards and needles that make repeated physical contact with the ICs under test. Such direct-contact probing is very costly and imposes limitations on the use of ATE. For example, the probe needles must be frequently cleaned or replaced, and some emerging technologies such as three-dimensional ICs cannot be probed at all. As an alternative to conventional probe-card testing, wireless testing has been proposed. It mitigates many of the foregoing problems by replacing probe needles and contact points with wireless communication circuits. However, wireless testing also raises new problems which are poorly understood such as: What is the most suitable wireless communication technique to employ, and how well does it work in practice? This dissertation addresses the design and implementation of circuits to support wireless testing of ICs. Various wireless testing methods are investigated and evaluated with respect to their practicality. The research focuses on near-field capacitive communication because of its efficiency over the very short ranges needed during IC manufacture. A new capacitive channel model including chip separation, cross-talk, and misalignment effects is proposed and validated using electro-magnetic simulation studies to provide the intuitions for efficient antenna and circuit design. We propose a compact clock and data recovery architecture to avoid a dedicated clock channel. An analytical model which predicts the DC-level fluctuation due to the capacitive channel is presented. Based on this model, feed-forward clock selection is designed to enhance performance. A method to select proper channel termination is discussed to maximize the channel efficiency for return-to-zero signaling. Two prototype ICs incorporating wireless testing systems were fabricated and tested with the proposed methods of testing digital circuits. Both successfully demonstrated gigahertz communication speeds with a bit-error rate less than 10^−11. A third prototype IC containing analog voltage measurement circuits was implemented to determine the feasibility of wirelessly testing analog circuits. The fabricated prototype achieved satisfactory voltage measurement with 1 mV resolution. Our work demonstrates the validity of the proposed models and the feasibility of near-field capacitive communication for wireless testing of ICs.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/93993/1/duelee_1.pd

Advanced Trends in Wireless Communications

Physical limitations on wireless communication channels impose huge challenges to reliable communication. Bandwidth limitations, propagation loss, noise and interference make the wireless channel a narrow pipe that does not readily accommodate rapid flow of data. Thus, researches aim to design systems that are suitable to operate in such channels, in order to have high performance quality of service. Also, the mobility of the communication systems requires further investigations to reduce the complexity and the power consumption of the receiver. This book aims to provide highlights of the current research in the field of wireless communications. The subjects discussed are very valuable to communication researchers rather than researchers in the wireless related areas. The book chapters cover a wide range of wireless communication topics

Optical generation of mm-wave signals for use in broadband radio over fiber systems

In future cellular radio networks Radio over Fiber (RoF) is a very attractive technology to deliver microwave and millimeter-wave signals containing broad band multimedia services to numerous base stations of the network. The radio signals are placed on an optical carrier and distributed by means of an optical fiber network to the base stations (BS). In the BS the optical signals heterodyne in a photodiode to produce the radio signals which are then sent via a wireless link to the mobile units (MU). The optical fiber network provides high frequency, wideband, low loss and a means of signal distribution immune to electromagnetic interference. In this thesis, different methods of electrooptical upconversion were investigated. The generation of an optical double-sideband with suppressed carrier (DSB-SC) signal is a straightforward method due to the fact that only one optical modulator driven at half the millimeter-wave frequency is required. One or both sidebands were ASK-modulated with baseband data rates of up to 10 Gbps. Optical single sideband modulation proves to be dispersion resilient as error free transmission was demonstrated after 53 km of single mode fiber transmission for data rates up to 10 Gbps. Wireless links up to 7 m were also demonstrated, proving the feasibility of this approach for broadband wireless inhouse access systems.Für zukünftige zellulare Funknetze ist „Radio over Fiber (RoF)“ eine sehr attraktive Technologie, um breitbandige Multimedia-Dienste mit Mikro- und Millimeterwellen zu übertragen. Die Funksignale werden dabei auf eine optische Trägerwelle aufmoduliert und mittels eines optischen Fasernetzes zu den Basisstationen (BS) verteilt. In den BS erfolgt die Überlagung der optischen Signale durch eine Fotodiode, um die Funksignale zu erzeugen. Diese werden dann über eine drahtlose Verbindung zu den beweglichen Multimedia-Endgeräten geschickt. Vorteile des optischen Fasernetzes sind Breitbandigkeit, geringe Dämpfung und eine gegenüber elektromagnetischen Störungen immune Signalverteilung. In dieser Arbeit werden verschiedene Methoden der elektrooptischen Aufwärtskonversion erforscht und die wichtigsten Eigenschaften dieser untersucht. Die Erzeugung eines optischen Zweiseitenbandsignales mit unterdrücktem Träger (DSB-SC) ist eine einfache Methode, da nur ein optischer Modulator, betrieben mit der halben elektrischen Trägerfrequenz, benötigt wird. Eine oder beide Seitenbänder konnten mit Bitraten bis zu 10 Gbps amplitudenmoduliert werden. Optische Einseitenbandmodulation ist extrem tolerant bezüglich der chromatischen Dispersion der Faser, wie die fehlerfreie Übertragung nach 53 km Glasfaser beweist. Drahtlose Links bis zu 7 m wurden realisiert und zeigen die Möglichkeit dieser Verfahren für breitbandige drahtlose Inhouse-Zugangssysteme

Shortest Route at Dynamic Location with Node Combination-Dijkstra Algorithm

Abstract— Online transportation has become a basic requirement of the general public in support of all activities to go to work, school or vacation to the sights. Public transportation services compete to provide the best service so that consumers feel comfortable using the services offered, so that all activities are noticed, one of them is the search for the shortest route in picking the buyer or delivering to the destination. Node Combination method can minimize memory usage and this methode is more optimal when compared to A* and Ant Colony in the shortest route search like Dijkstra algorithm, but can’t store the history node that has been passed. Therefore, using node combination algorithm is very good in searching the shortest distance is not the shortest route. This paper is structured to modify the node combination algorithm to solve the problem of finding the shortest route at the dynamic location obtained from the transport fleet by displaying the nodes that have the shortest distance and will be implemented in the geographic information system in the form of map to facilitate the use of the system. Keywords— Shortest Path, Algorithm Dijkstra, Node Combination, Dynamic Location (key words